The test of time. Clock-cycle estimation and test challenges forfuture microprocessors

Even with aggressive new technology, the complex high-performance processor will require special design techniques and architectures to take advantage of new interconnect and transistor technology. Microprocessor on-chip clock frequencies of multiple GHz are predicted for future generations. However, significant development is necessary in technology, manufacturing, and design CAD tools in order to achieve the performance, manufacturability, and reliability desired for these future products. Design must own the test function. The ability of test to continue supporting at-speed testing has reached physical limits as well as cost impacts that will make testing a very high design priority     

Avoiding engineering changes through focused manufacturingknowledge

An exploratory analysis of how product-development engineers can avoid many manufacturability-related engineering changes (ECs) if they develop focused manufacturing knowledge is described. An engineer would develop focused manufacturing knowledge by working in an existing area of manufacturing most related to that engineer's development task. The occurrence of ECs that are avoidable with focused manufacturing knowledge does not justify that all product development engineers gain this knowledge. However, engineers who design components with a significant history of manufacturability problems should develop this knowledge to achieve the benefits of EC avoidance. It is concluded that organizations should manage the development of focused manufacturing knowledge     

VLSI: linking design and manufacturing

A set of computer-aided design (CAD) tools that predict the effects of various manufacturing steps along with the chip's internal dimensions is described. Called the Process Engineer's Workbench, the system predicts the chip's characteristics, their statistical distribution, and the manufacturing yield likely from any one fabrication process. The tools are even sensitive to the small random variations that increase in significance as devices shrink in size. Workbench can be used to compare its programs' predictions and those of other software tools with actual measurements of devices and processes. Some existing CAD tools are reviewed to highlight the Workbench's advantages, and the features of the latter are examined. Written in C language for a Digital Equipment VAXstation, Workbench was designed to be portable and runs on several other popular workstations. It contains two basic libraries, namely, one of device models, the other of process step models     

Power conscious CAD tools and methodologies: a perspective

Power consumption is rapidly becoming an area of growing concern in IC and system design houses. Issues such as battery life, thermal limits, packaging constraints and cooling options are becoming key factors in the success of a product. As a consequence, IC and system designers are beginning to see the impact of power on design area, design speed, design complexity and manufacturing cost. While process and voltage scaling can achieve significant power reductions, these are expensive strategies that require industry momentum, that only pay off in the long run. Technology independent gains for power come from the area of design for low power which has a much higher return on investment (ROI). But low power design is not only a new area but is also a complex endeavour requiring a broad range of synergistic capabilities from architecture/microarchitecture design to package design. It changes traditional IC design from a two-dimensional problem (Area/performance) to a three-dimensional one (Area/Performance/Power). This paper describes the CAD tools and methodologies required to effect efficient design for low power. It is targeted to a wide audience and tries to convey an understanding of the breadth of the problem. It explains the state of the art in CAD tools and methodologies. The paper is written in the form of a tutorial, making it easy to read by keeping the technical depth to a minimum while supplying a wealth of technical references. Simultaneously the paper identifies unresolved problems in an attempt to incite research in these areas. Finally an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design     

用陶瓷厚膜埋入无源元件进行设计：填补两大空白

埋入无源元件(即被精确制入PCB基板的电阻器和电容器)将是PCB工业下一项关键性技术。但是,PCB制造厂商和设计人员首先必须填补设计与元件制造之间的空白,必须填补设计与可用CAD工具之间的空白。     

集成电路可制造性工程与设计方法学

集成电路可制造性工怀设计是近年来发展很快的研究领域，它集ＩＣ设计、制造、封装和测试过程为一体，在统一框图（即产品制造成本和成品率驱动下）下，对产品进行规划和设计，应用该设计可以大大缩短ＩＣ产品研制周期，降低制造成本，提高成品率和可靠性，本文将综述该领域的研究进展，并阐述进一步的研究方向。     

Statistical computer-aided design for microwave circuits

A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making “designing for circuit manufacturability” a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology     

Variation

Variation afflicts the design, manufacture, and operation of integrated circuits. Techniques and tools are needed in three areas to address variation: statistical metrology, advanced process control, and design for manufacturability. First, statistical metrology seeks to characterize and model variations and their sources. Advanced metrology helps to understand geometric and material property variations, while variation test structures and test circuits enable study of the impact of specific or aggregate variations on performance. Second, advanced process control attempts to reduce process variation through sensing and feedback/feedforward control during fabrication. Third, design for manufacturability (DFM) seeks methods to improve performance and yield given process and environmental variation, through robust design, increased regularity, and other approaches. Finally, linkages between these areas, particularly between statistical metrology and DFM, will be important and empowering.     

The hidden professionals: product designers and their impact ondesign quality

The authors discuss the roles of designers in the development engineering phase of product development and examine the effects of designer communication, job design, organization climate, and CAD system quality on design quality. A survey of designers and design engineers at ten manufacturing sites was conducted. Communication with downstream processes, task significance, and job commitment was associated with greater achievement of manufacturability objectives. Communication with downstream processes and within the design core team was associated with achievement of strength objectives. Job commitment was a significant predictor of achievement of cost objectives. CAD system quality was not associated with any of the outcome measures. These results suggest that managers of development engineering organizations should treat designers more as professionals and less as workers. They should also redesign the jobs of both designers and design engineers to insure that the designers have greater responsibility and authority for linking with external groups     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

A new device design methodology for manufacturability

As future technology generations for integrated circuits continue to “shrink”, TCAD tools must be made more central to manufacturing issues; thus, yield optimization and design for manufacturing (DFM) should be addressed integrally with performance and reliability when using TCAD during the initial product design. This paper defines the goals for DFM in TCAD simulations and outlines a formal procedure for achieving an optimized result (ODFM). New design of experiments (DOE), weighted least squares modeling and multiple-objective mean-variance optimization methods are developed as significant parts of the new ODFM procedure. Examples of designing a 0.18-μm MOSFET device are given to show the impact of device design procedures on device performance distributions and sensitivity variance profiles     

Yield constrained automated design algorithm for power optimized pipeline ADC

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit pipeline ADC is designed and analyzed. This ADC has 10-bit resolution and 6.3 mW power, 91% yield, 55.3 dB SNDR and 58.8 dB SFDR, which are all in good agreement with the algorithm results. In comparison with similar designs it offers a competitive Figure of Merit (FOM), which proves the capability of this algorithm in finding the optimum solution.     

Analysis of mixed-signal manufacturability with statisticaltechnology CAD (TCAD)

We have developed a methodology which combines technology CAD (TCAD) simulation with statistical analysis of empirical data to predict and control the manufacturability of IC fabrication processes. As a result, manufacturing tolerance or sigma-based models (also known as worst-case models) can be determined before a significant sample size of fabricated devices can be characterized. Early on in the development cycle, empirical data is collected, and models built from simulated data are refined. These revised models are used to determine process control limits, and optimize in-line and electrical test measurement (E-test) for maximum observability of variation. As the process is stabilized, further refined models are used to perform yield diagnosis and tolerance analysis of circuits. This methodology has been applied to a number of BJT and submicrometer CMOS processes to create predictive sigma-based models, modify the fabrication recipe to meet objective specifications as development proceeds, and finally use them to control the manufacturing line     

Routing for manufacturability and reliability

As IC process geometries scale down to the nanometer territory, industry faces severe challenges of manufacturing limitations. To guarantee high yield and reliability, routing for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this article, we introduce major routing challenges arising from nanometer process, survey key existing techniques for handling the challenges, and provide some future research directions in routing for manufacturability and reliability.     

Layout-synthesis techniques for yield enhancement

Several yield-enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modifications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and the yield improvement results of some industrial layout examples are shown. This algorithm has been implemented in a commercial CAD framework. Some routing techniques for wire length and via minimization are presented, and the results of wire length reduction in benchmark routing examples are shown. We demonstrate through topological optimization for PLA-based designs that yield enhancement can be applied even at a higher level of design abstraction. Experimental results show that it is possible to achieve significant yield improvements without increasing the layout area by applying the proposed techniques during layout synthesis     

A New Approach to Abstracting AltPSM Lithography Requirements for IC Design Domains

This paper lays the groundwork for defining the components needed to get clean alternating phase-shifting masks (altPSM) that ensure the manufacturability of subwavelength circuit designs. The authors create an abstract set of rules that can be used to advantage in various IC CAD tool domains. A new methodology and algorithm are presented that can quickly and easily integrate altPSM into existing and future tools earlier in the IC design flow. Finally, experimental results show how the methodology and algorithm is used to debug process-aware designs and make them altPSM-compliant.Pradiptya Ghosh has a M.S. (Computer and System Engg) from Rensselaer Polytechnic Institute, New York and a B.Engg (Computer Engineering) from Delhi University, India. He is currently working on physical syntesis tool for FPGA. Previously he has worked on alternating PSM methodology and developed tools for integrating it into DFM flow. He has worked on timing and routability driven RTL floorplanning for his thesis. He did some work on global routing algorithms and their application to datapaths at SUN Microsystems and have couple of patents on them. He has also been an architect for the CAD framework and datamodel at Sun Microsystems and have couple of patent pending in that domain. He has also worked previously at Cadence at board level tool development and at Intel prototyping a floorplanning tool.     

Tools for the computer-aided design of multigigahertzsuperconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented     

Mining metadata for composability of IPs from SystemC IP library

Exploring the design space when constructing a system is vital to realize a well performing design. Design complexity has made building high-level system models to explore the design space an essential but time-consuming and tedious part of the system design. Reduction in design time and acceleration of design exploration can be provided through reusing IP-cores to construct system models. As a result, it is common to have high-level SoC design flow based on IP libraries promoting reuse. However, the success of these would be dependent on how introspection and reflection capabilities are provided as well as what are the interoperability standard defined. This leads to the important question of what kind of IP metadata must be available to allow CAD tools to effectively manipulate these designs as well as allow for a seamless integration and exchange design information between tools and design flows. In this article, we describe our tools and methodology, which allow introspection of SystemC designs, such that the extracted metadata enables IP composition. We discuss the issues related to extraction of metadata from IPs specified in SystemC and show how our methodology combines C++ and XML parsers and data structures to achieve the above.     

Device CAD in the '90s: at the crossroads

Various issues concerning technology computer-aided design (TCAD), including fundamental research, practical issues of user friendliness, experimental verification, and framework initiatives are discussed. The focus is on device CAD, in which there is a continuing shift of emphasis from basic issues of device physics and engineering to questions of manufacturability and technology scalability. The automation of input, computational mesh, and electrical biasing information generation in TCAD systems is described. The visualization and interpretation of simulated results, the advent of new computer hardware, and the use of statistical simulations in TCAD technology are discussed. It is argued that while technology experts are willing to tolerate awkwardness in a TCAD system, new users of TCAD, such as circuit designers and manufacturing engineers, demand automation, robustness, and reliability as standard features