Silicon-carbide high-voltage (400 V) Schottky barrier diodes

The authors describe the fabrication and characteristics of the first high-voltage (400-V) silicon-carbide (6H-SiC) Schottky barrier diodes. Measurements of the forward I-V characteristics of these diodes demonstrate a low forward voltage drop of ~1.1 V at an on-state current density of 100 A/cm² for a temperature range of 25 to 200°C. The reverse I-V characteristics of these devices exhibit a sharp breakdown, with breakdown voltages exceeding 400 V at 25°C. In addition, these diodes are shown to have superior reverse recovery characteristics when compared with high-speed silicon P-i-N rectifiers     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

Ultradry annealing after polysilicon electrode formation forimproving the TDDB lifetime of ultrathin silicon oxide films in MOSdiodes

Effects of ultradry annealing on time-dependent dielectric breakdown (TDDB) lifetime (T_TDDB) were investigated for Si MOS diodes with 5-nm-thick silicon oxide and P-doped polysilicon gate electrode films. This annealing was performed at 800°C in ultradry N₂ of less than 1-ppm moisture concentration after the electrode formation. Under an accumulation-bias stress condition, T_TDDB for the ultradry-annealed n-type Si diodes was larger than that for the conventionally annealed ones, while such T _TDDB enhancement was not confirmed in the p-type ones. Since positive charges induced near anode-side oxide interfaces are closely related to T_TDDB, the T_TDDB enhancement for the ultradry-annealed n-type Si diodes probably reflects a qualitative improvement of the anode-side, i.e., gate-electrode-oxide, interfaces by ultradry annealing     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions     

The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V_d =8 V and V_g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V_b), having a power-law gradient of 0.5 for V_b=0 V and 0.3 for V_b=-9 V. Investigation of the type of damage resulting from stressing shows that at V_b=0 V, interface state generation results, while at V_b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions     

A model for the temperature-dependent saturated ID-VD characteristics of an a-Si:H thin-filmtransistor

A simplified analytical expression for the temperature dependent saturated I_D-V_D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I_D versus V_G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I_D and more severe gate voltage hysteresis characteristics     

High-transconductance insulating-gate InP/InGaAs buried p-bufferDH-MODFETs grown by MOVPE

Buried p-buffer double heterostructure modulation-doped field-effect transistors (BP DH-MODFETs) with an InGaAs quantum-well channel were fabricated with high transconductance and good breakdown voltage, by placing the metal gate directly on Fe-doped InP insulating layer. Excellent extrinsic DC transconductance of 560 mS/mm and a high gate-to-drain diode breakdown voltage (greater than 20 V) were achieved at room temperature with FETs of 1.2-μm gate length. Unity currently gain cutoff frequency f_T of 24 GHz and maximum oscillation frequency f_max of 60 GHz were demonstrated for a drain to source voltage V_DS=4 V, which corresponds to an average electron velocity of 2.2×10⁷ cm/s in the quantum well     

AlGaAs and GaAsP high-power ultrafast p+-n-n+diodes based on heterojunctions and a graded-gap base

The authors present a theoretical model of power p⁺-n-n ⁺ diodes with a graded-gap base and either homojunctions (GB) or heterojunctions (HGB), and numerical calculations of static and dynamic characteristics of AlGaAs (GaAsP) based structures. It is shown that HGB diodes will exhibit characteristics and properties significantly better than those of simple (homojunctions plus uniform base) GaAs and Si diodes. For example, the forward voltage drop in a high-voltage (W/L_p=13) high-frequency (t_rr=25 ns) HGB diode will be 50% and 300% smaller than the drop in, respectively, simple GaAs and Si diodes with the same W/L_p and t_rr. Other significant projected improvements include operation up to 450°C, an order of magnitude reduction in the reverse current, and a 50% increase in the breakdown voltage     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

A multiple-state memory cell based on the resonant tunneling diode

The device consists primarily of several molecular-beam-epitaxy (MBE-) grown GaAs/(AlGa)As resonant tunneling diodes connected in parallel. This device exhibits multiple peaks in the I-V characteristic. When a load resistor is connected, the circuit can be operated in a multiple stable mode. With this concept, implementation of three-state and four-state memory cells are made. In the three-state case the operating points at voltages V₀=0.27 V , V₁=0.42 V, and V₂=0.53 V represent the logic levels 0, 1, and 2. Similarly for the four-state memory cell the logic levels voltages are V₀=0.35 V, V₁=0.42 V, V₂=0.54 V, and V ₃=0.59 V. A suggestion of an integrated device structure using this concept is also presented     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

Self-heating effects in basic semiconductor structures

Investigates the effects of self-heating on the high current I -V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T_i to 3T_i , where T_i is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T_i is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed