HKMG CMOS technology qualification: The PBTI reliability challenge

We present a brief overview of Positive Bias Temperature Instability (PBTI) commonly observed in n-channel MOSFETs with SiO₂/HfO₂/TiN dual-layer gate stacks when stressed with positive gate voltage at elevated temperatures. We review the origin and present understanding of the characteristics of oxide traps that are responsible for the complex behavior of threshold voltage stability. We discuss the various physical mechanisms that are believed to govern the transient charging and discharging of these traps as the backbone of the models that have been proposed for PBTI degradation and recovery. Next we review the state-of-the-art in PBTI characterization and we present some of the key stress results on both the device as well the circuit level. Special emphasis is given on the open PBTI issues that need to be carefully addressed for a robust reliability methodology that accurately predicts PBTI lifetimes. Finally we mention some of the gate stack scaling effects on PBTI.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

Early detection and prediction of HKMG SRAM HTOL performance by WLR PBTI tests

With technologies scaling down to 28 nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO₂ film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.     

Identification of electron trap location degrading low-frequency noise and PBTI in poly-Si/HfO2/interface-layer gate-stack MOSFETs

Identification of electron trap location in HfO₂/interface-layer (IFL) of poly-Si/TiN/HfO₂/SiO₂ gate-stacked MOSFETs is successfully demonstrated through analysis of low-frequency noise and PBTI characteristics with respect to nitrogen incorporation into the gate dielectrics in fabrication process. It is found that the electron trap existing in the bulk-IFL dominantly degrades low-frequency noise (LFN) and positive bias temperature instability (PBTI). The pre-existing electron trap is considered to be generated by N incorporation into the IFL in the fabrication process of gate-first process.     

Control of Interface Traps in HfO2 Gate Dielectric on Silicon

The effects of postdeposition annealing (PDA) on the interface between HfO₂ high-k dielectric and bulk silicon were studied in detail. The key challenges of successfully adopting the high-k dielectric/Si gate stack into advanced complementary metal–oxide–semiconductor (CMOS) technology are mostly due to interfacial properties. We have proposed a PDA treatment at 600°C for several different durations (5 min to 25 min) in nitrogen or oxygen (95% N₂ + 5% O₂) ambient with a 5-nm-thick HfO₂ film on a silicon substrate. We found that oxidation of the HfO₂/Si interface, removal of the deep trap centers, and crystallization of the film take place during the postdeposition annealing (PDA). The optimal PDA conditions for low interface trap density were found to be dependent on the PDA duration. The formation of an amorphous interface layer (IL) at the HfO₂/Si interface was observed. The growth was due to oxygen incorporated during thermal annealing that reacts with the Si substrate. The interface traps of the bonding features, defect states, and hysteresis under different PDA conditions were studied using x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), transmission electron microscopy (TEM), and leakage current density–voltage (J–V) and capacitance–voltage (C–V) techniques. The results showed that the HfO₂/Si stack with PDA in oxygen showed better physical and electrical performance than with PDA in nitrogen. Therefore, PDA can improve the interface properties of HfO₂/Si and the densification of HfO₂ thin films.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

Oxygen vacancy induced charge trapping and positive bias temperature instability in HfO2nMOSFET

The charge trapping and positive bias temperature instability (PBTI) are investigated at different post deposition annealing conditions (PDA) in HfO₂ nMOSFET. Pulse based measurements (Pulsed Id-Vg and “Pulse on the fly”) are performed to characterize charge trapping effect. Compared with NH₃ PDA, the NH₃ + O₂ PDA shows significant reduction of charge trap sites in HfO₂, which causes the improvement of device performance and reliability. The significant improvement after additional annealing can be explained by the passivation of oxygen vacancies in HfO₂.     

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation is provided by using modified charge-pumping (CP) techniques. The original distribution of interface traps and bulk traps of pure HfO₂ and HfO₂/LaOx dielectric stack are extracted and compared by CP techniques. It is found that devices with HfO₂/LaOx dielectric stack have higher interface trap but lower bulk trap density than those with pure HfO₂. Especially, device with HfO₂/LaOx dielectric stack is highly resistant to constant voltage stress, which can be attributed to the suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation.     

On the dynamic NBTI of the HfO2 and HfSiON P-MOSFET

Under typical dynamic NBTI conditions (∼7 MV/cm, 100 °C), a progressive decrease in the recoverable component (R) of the HfO₂ p-MOSFET is observed but those of the HfSiON and SiON p-MOSFETs are found to remain constant. The decrease in the R of the HfO₂ p-MOSFET is shown to be a result of its conversion into a permanent form. Under a given oxide field and temperature, the R of the HfO₂ p-MOSFET is found to exhibit the greatest tendency to be converted into a permanent form. This behavior is shown to be related to the evolution of hole traps in the HfO₂ and could be explained in terms of the generally more ionic character of high-κ dielectrics.     

Intrinsic bonding defects in transition metal elemental oxides

Gate dielectrics comprised of nanocrystalline HfO₂ in gate stacks with thin SiO₂/SiON interfacial transition regions display significant asymmetries with respect to trapping of Si substrate injected holes and electrons. Based on spectroscopic studies, and guided by ab initio theory, electron and hole traps in HfO₂ and other transition metal elemental oxides are assigned to O-atom divacancies, clustered at internal grain boundaries. Three engineering solutions for defect reduction are identified: i) deposition of ultra-thin, <2 nm, HfO₂ dielectric layers, in which grain boundary formation is suppressed by effectively eliminating inter-primitive unit cell π-bonding interactions, ii) chemically phase separated high HfO₂ silicates in which inter-primitive unit cell p-bonding interactions are suppressed by the two nanocrystalline grain size limitations resulting from SiO₂ inclusions, and iii) non-crystalline Zr/Hf Si oxynitrides without grain boundary defects.     

Impact of Hf content on positive bias temperature instability reliability of HfSiON gate dielectrics

Metal-oxide-semiconductor field-effect transistors (MOSFETs) incorporating HfSiON dielectrics with different compositions have been fabricated using atomic layer deposition (ALD) and their positive bias temperature instability (PBTI) reliability has also been investigated. The experimental results indicate that the oxide trapped charge (N_ot) dominates the PBTI degradation process, and after PBTI stress the increment of oxide trapped charges (ΔN_ot) is about 2-3 orders of magnitude greater than the generation of interface traps (ΔN_it). Moreover, higher Hf concentration results in more pre-existing traps but slower trap creation rate. The charge pumping technique has been utilized to characterize the interfacial parameters, ΔN_it, ΔN_ot, and ΔD_it (the generation of the density of interface trap per energy and area).     

Electrical characterization of hafnium oxide and hafnium-rich silicate films grown by atomic layer deposition

An electrical characterization comparative analysis between Al/HfO₂/n-Si and Al/Hf-Si-O/n-Si samples has been carried out. Hafnium-based dielectric films have been grown by means of atomic layer deposition (ALD). Interface quality have been determined by using capacitance–voltage (C–V), deep level transient spectroscopy (DLTS) and conductance transient (G-t) techniques. Our results show that silicate films exhibit less flat-band voltage shift and hysteresis effect, and so lower disordered induced gap states (DIGS) density than oxide films, but interfacial state density is greater in Hf–Si–O than in HfO₂. Moreover, a post-deposition annealing in vacuum under N₂ flow for 1 min, at temperatures between 600 and 730 °C diminishes interfacial state density of Hf–Si–O films to values measured in HfO₂ films, without degrade the interface quality in terms of DIGS.     

采用电子束蒸发方法结合一步快速退火制备的Ni-FUSI栅性能研究

本文采用高真空电子束蒸发方法在HfO2栅介质上依次沉积了Si膜与Ni膜并结合一步快速退火制备了Ni基全硅化物金属栅（Ni-FUSI)。X射线衍射和拉曼光谱结果表明经过快速退火处理金属栅完成了硅化反应其主相为镍硅化物相。我们通过制备Ni-FUSI/ HfO2 /Si结构(MIS)电容研究了NiSi栅的电学性能。测得的C-V曲线积累区曲线平坦,从积累区到反型区界面陡峭,滞回电压很小,提取的NiSi功函数为5.44eV~5.53eV。MIS电容漏电流很小,在栅压为-1V时漏电流密度只有1.45?10-8A/cm-2。     

Non-ideal effects improvement of SF6 plasma treated hafnium oxide film based on electrolyte-insulator-semiconductor structure for pH-sensor application

A novel HfO₂ thin film with SF₆ plasma treatment as ion selective membrane on electrolyte-insulator-semiconductor structure for pH-sensor was proposed. The sensing characteristics on hydrogen ion detection and the non-ideal effects including drift effect, hysteresis phenomenon, and responses on interference ions were all presented in this article. The results show that the slight increase of pH-sensitivity is achieved and the non-ideal effects are improved after SF₆ plasma treatment. It is finally concluded that the HfO₂ thin film with SF₆ plasma treatment as ion selective membrane is suitable for pH detection and the optimum condition is 5 min for SF₆ plasma treatment.     

Impact of nitrogen incorporation on interface states in (1 0 0)Si/HfO2

The energy distribution of (1 0 0)Si/HfO₂ interface states and their passivation by hydrogen are studied for different levels of nitrogen incorporation using different technological methods. The results are compared to those of N-free samples. The nitrogen in the (1 0 0)Si/HfO₂ entity is found to increase the trap density in the upper part of the Si band gap and to hinder the passivation of traps in molecular hydrogen in this energy range. At the same time, the passivation of fast interface traps in the lower part of the band gap proceeds efficiently, provided the thickness of the grown Si₃N₄ interlayer is kept minimal. However, the lowest achievable interface trap density below midgap is set by the presence of slow N-related states, likely related to traps in the insulator.     

Hafnium oxide thin films deposited by high pressure reactive sputtering in atmosphere formed with different Ar/O2 ratios

The physical and electrical properties of hafnium oxide (HfO₂) thin films deposited by high pressure reactive sputtering (HPRS) have been studied as a function of the Ar/O₂ ratio in the sputtering gas mixture. Transmission electron microscopy shows that the HfO₂ films are polycrystalline, except the films deposited in pure Ar, which are amorphous. According to heavy ion elastic recoil detection analysis, the films deposited without using O₂ are stoichiometric, which means that the composition of the HfO₂ target is conserved in the deposition films. The use of O₂ for reactive sputtering results in slightly oxygen-rich films. Metal-Oxide-Semiconductor (MOS) devices were fabricated to determine the deposited HfO₂ dielectric constant and the trap density at the HfO₂/Si interface (D_it) using the high–low frequency capacitance method. Poor capacitance–voltage (CV) characteristics and high values of D_it are observed in the polycrystalline HfO₂ films. However, a great improvement of the electrical properties was observed in the amorphous HfO₂ films, showing dielectric constant values close to 17 and a minimum D_it of 2×10¹¹ eV⁻¹ cm⁻².     

Organic thin film transistors with HfO2 high-k gate dielectric grown by anodic oxidation or deposited by sol–gel

We report here on pentacene based organic field effect transistors (OFETs) with a high-k HfO₂ gate oxide. HfO₂ layers were prepared by two different methods: anodic oxidation and sol–gel. A comparison of the two processes on the electrical properties of OFETs is given. Ultra thin nanoporous (20 nm) sol–gel deposited oxide films were obtained following an annealing at 450 °C. They lead to high mobility and stable devices (μ = 0.12 cm²/V s). On the other hand, devices with anodic HfO₂ revealed a little bit more leaky and show some hysteresis. Anodization, however, presents the advantage of being a fully room temperature process, compatible with plastic substrates. Stability and response to a bias stress are also reported.     

Optical and electrical characterization of hafnium oxide deposited by MOCVD

The paper reports on electrical and optical investigations performed on HfO₂ high-k films deposited by Metal-organic chemical vapor deposition (MOCVD). Spectroellipsometry investigations show the presence of a transition layer between HfO₂ and the silicon substrate, which can be optically modelled as a mixture of Si and SiO₂; this information is further used in the assessment of the electrical measurements. Hysteresis effects have been observed in the Capacitance–Voltage (C–V) measurements for the as-deposited sample as well as the annealed samples. For the samples with large hysteresis, Poole–Frenkel (PF) conduction is the most likely dominant conduction mechanism. The energy of dominant trap level was found to be 0.7 eV.     

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO₂ nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t_L = 1.64 × 10¹⁰ s, which agreed well with the t_L = 1.92 × 10¹⁰ s measured at low gate stress voltage, whereas the conventional model overestimates t_L by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t_L of high-k nMOSFETs.