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1.
High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device. 相似文献
2.
Chan A.B.Y. Nguyen C.T. Ko P.K. Chan S.T.H. Wong S.S. 《Electron Devices, IEEE Transactions on》1997,44(3):455-463
Chemical-mechanical polishing (CMP) has been applied to the fabrication of n-channel polysilicon thin film transistors (poly-Si TFT's). Three different polishing conditions are compared: (1) polishing before; (2) polishing after; and (3) both polishing before and after the a-Si recrystallization. Devices with no polishing act as control samples. Experiments consistently reveal that devices with post-anneal polishing exhibit the best performance, Two-fold improvement of drain current is attributed to the smoother active polysilicon surface. The electrical characteristics of a post-anneal polished TFT in terms of field effect mobility μFE, threshold voltage VT, and subthreshold swing S can be further improved if hydrogenation is employed. It is also found that a large decrease in the poly-Si surface roughness leads to higher dielectric breakdown strength and improved short-channel effects. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) results are presented and correlated with electrical results 相似文献
3.
首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术. 相似文献
4.
首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术. 相似文献
5.
6.
A novel omega-shaped-gated (Ω-Gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Ω-Gate structure inherently covered two sharp corners manufactured simply via a sidewall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Ω-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Ω-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Ω-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications. 相似文献
7.
Qiuxia Xu He Qian Huaxiang Yin Lin Jia Honghao Ji Baoqing Chen Yajiang Zhu Min Liu Zhensheng Han Huanzhang Hu Yulin Qiu Dexin Wu 《Electron Devices, IEEE Transactions on》2001,48(7):1412-1420
The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p+/n+ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved 相似文献
8.
Juang Miin-Horng Chang Chia-Wei Shye Der-Chih Hwang Chuan-Chou Wang Jih-Liang Jang Sheng-Liang 《半导体学报》2010,31(6):064003-064003-5
A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration. 相似文献
9.
Won-Kyu Lee Joong-Hyun Park Joonhoo Choi Min-Koo Han 《Electron Device Letters, IEEE》2008,29(2):174-176
We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n+ amorphous silicon (n+ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (VTH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm2/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P+ ions) in the channel reduced the VTH and increased the S value. 相似文献
10.
Po-Sheng Shih Chun-Yen Chang Ting-Chang Chang Tiao-Yuan Huang Du-Zen Peng Ching-Fa Yeh 《Electron Device Letters, IEEE》1999,20(8):421-423
We have proposed and successfully demonstrated a novel process for fabricating lightly doped drain (LDD) polycrystalline silicon thin-film transistors (TFT's). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) oxide performed at 23°C. Devices fabricated with the new process exhibit a lower leakage current and a better ON/OFF current ratio than non-LDD control devices. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be quite promising for future high-performance poly-Si TFT fabrication 相似文献
11.
A planar type polysilicon thin-film transistor (poly-Si TFT) EEPROM cell with electron cyclotron resonance (ECR) N2O-plasma oxide has been developed with a low temperature (⩽400°C) process. The poly-Si TFT EEPROM cell has an initial threshold voltage shift of 4 V for programming and erasing voltages of 11 V and -11 V, respectively. Furthermore, the poly-Si TFT EEPROM cell maintains the threshold voltage shift of 4 V after 100 000 program/erase cycles. The excellent high endurance of the fabricated poly-Si TFT EEPROM cell is attributed to the ECR N2O-plasma oxide with good charge-to-breakdown (Qbd) characteristics 相似文献
12.
Summer F. C. Tseng Wei-Ting Kary Chien Bing-Chu Cai 《Microelectronics Reliability》2003,43(5):713-724
This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH4) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes. 相似文献
13.
A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator
We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiNx ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiNx and laser annealed poly-Si. After patterning thin a-Si:H/SiNx layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n+ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm2/Vs and a threshold voltage of 1 V 相似文献
14.
A New Poly-Si TFT Current-Mirror Pixel for Active Matrix Organic Light Emitting Diode 总被引:1,自引:0,他引:1
《Electron Device Letters, IEEE》2006,27(10):830-833
A new poly-Si thin-film-transistor (TFT) current-mirror-active-matrix-organic-light-emitting-diode (AMOLED) pixel, which successfully compensates for the variation of the threshold voltage as well as mobility in the excimer laser annealed poly-Si TFT pixel, is designed and fabricated. The OLED current$(I_ OLED)$ of the proposed pixel does not depend on the operating temperature. When the temperature of pixel is increased from 27$^circhboxC$ to 60$^circhboxC$ , the$I_ OLED$ of the new pixel circuit composed of four TFTs and one capacitor increases only about 1.5%, while that of a conventional pixel composed of two TFTs and one capacitor increases about 37%. At room temperature, nonuniformity of the$I_ OLED$ in the proposed circuit was also considerably suppressed at around 9%. We have successfully fabricated a 1.2-in AMOLED panel$(hbox96 times hbox96 times hboxred green blue)$ to evaluate the performance of the proposed pixel. A troublesome residual image caused by the hysteresis phenomenon of the poly-Si TFT was almost eliminated in the proposed AMOLED panel as a result of current programming. 相似文献
15.
Huang-Chung Cheng Fang-Shing Wang Chun-Yao Huang 《Electron Devices, IEEE Transactions on》1997,44(1):64-68
The NH3-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH3-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 108, and also better hot-carrier reliability than the H2-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO2/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH3-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's 相似文献
16.
Polycrystalline silicon-germanium thin-film transistors 总被引:3,自引:0,他引:3
The fabrication of p- and n-channel MOS thin-film transistors (TFT's) in polycrystalline silicon-germanium (poly-Si1-xGe x) films is described, and their electrical characteristics are presented. Various technological issues are then addressed in order to provide direction for further work in optimizing the fabrication process. The initial devices fabricated in this work exhibit well behaved electrical characteristics; enhanced performance is expected to accompany improvements in the crystallization and defect-passivation processes. Compared to a poly-Si TFT technology, an optimized poly-Si 1-xGex TFT technology may ultimately be able to provide a lower-temperature, shorter-time processing capability at little expense to device performance and it is therefore promising for large-area electronics applications 相似文献
17.
低温多晶硅(LTPS:Low-temperature poly-Si)技术已经成为薄膜晶体管(TFT:thin film transistor)制作中最具吸引力的技术,并应用在AMOLED显示器中.P-type 技术能够简化 TFT 的制作过程.本文提出了一种应用 p-type 多晶硅 TFT的 AMOLED 驱动电路结构,包括栅极驱动器、数据驱动器以及像素阵列.数据驱动器采用分块方法,使得显示屏的输出线数大大减少.作者采用一种改进的 p-type 移位寄存器实现逐行选通的功能,并采用由 4 个 p-type 反相器级联构成的缓冲器来提高电路的驱动能力.为了验证上述电路结构的正确性,作者采用 HSPICE 软件进行仿真分析.结果表明,电路工作正常.利用韩国汉城国立大学及 Neo Poly 公司在多晶硅制作方面的优势,我们已经合作完成了应用上述电路结构的分辨率为96×3×128的有源 OLED 的制作. 相似文献
18.
Using Phosphorus-Doped α-Si Gettering Layers to Improve NILC Poly-Si TFT Performance 总被引:1,自引:0,他引:1
Ni-metal-induced lateral crystallization (NILC) has been utilized to fabricate polycrystalline silicon (poly-Si) thin-film
transistors (TFTs). However, the current crystallization technology often leads to trapped Ni and NiSi2 precipitates, thus degrading device performance. In this study, phosphorus-doped amorphous silicon (p-α-Si) and chemical
oxide (chem-SiO2) films were used as Ni-gettering layers. After a gettering process, the Ni impurity within the NILC poly-Si film and the
leakage current were both reduced, while the on/off current ratio was increased. This gettering process is compatible with
NILC TFT processes and suitable for large-area NILC poly-Si films. 相似文献
19.
Chung S.S. Shui-Ming Cheng Lee R.G.-H. Song-Nian Kuo Mong-Song Liang 《Electron Devices, IEEE Transactions on》1997,44(12):2220-2226
This paper reports a simple I-V method for the first time to determine the lateral lightly-doped source/drain (S/D) profiles (n- region) of LDD n-MOSFETs. One interesting result is the direct observation of the reverse-short-channel effect (RSCE). It is observed that S/D n- doping profile is channel length dependent if reverse short-channel effect exists as a result of the interstitial imperfections caused by Oxide Enhanced Diffusion (OED) or S/D implant. Not only the lateral profiles for long-channel devices but also for short-channel devices can be determined. One other practical application of the present method for device drain engineering has been demonstrated with a LATID MOS device drain engineering work. It is convincible that the proposed method is well suited for the characterization and optimization of submicron and deep-submicron MOSFETs in the current ULSI technology 相似文献
20.
《Electron Devices, IEEE Transactions on》2008,55(9):2417-2422