A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

Low-power low-voltage reference using peaking current mirror circuit

A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 /spl mu/m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm//spl deg/C, the supplied current 2.3 /spl mu/A, and the power supply noise rejection ratio of -84 dB at 1 kHz.     

An integrated bandgap reference

Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise. A bread-board model of this configuration has been tested. In the temperature range of 0-70/spl deg/C, the output voltage variations were less than /spl plusmn/70 ppm at an output voltage of about 2.5 V and zero load current. Low-frequency noise in a bandwidth 0.003 Hz相似文献   

5 V temperature regulated voltage reference

A 5 V internally temperature regulated voltage reference integrated circuit, which achieves 0.3 ppm//spl deg/C TC over the temperature range -55/spl deg/C to 125/spl deg/C, is described. It is built using a buried zener reference in a dielectrically isolated complementary bipolar process which employs laser trimmed NiCr thin film resistors and a high thermal resistance epoxy die attach.     

A complete high-speed voltage output 16-bit monolithic DAC

A new single-chip 16-bit monolithic digital/analog converter (DAC) with on-chip voltage reference and operational amplifiers has achieved /spl plusmn/0.0015% linearity, 10 ppm//spl deg/C gain drift, and 4-/spl mu/s settling time. Novel elements of the 16-bit DAC include: the fast settling open-loop reference with a buried Zener, a fast-settling output operational amplifier without the use of feedforward compensation, and a modified R-2R ladder network. Thermal considerations played a significant role in the design. The DAC is fabricated using a 20-V process to reduce device sizes and therefore die size. All laser trimming including temperature drift compensation is performed at the wafer level. The converter does not require external components for operation.     

A new curvature-corrected bandgap reference

A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V.     

A very high precision 500-nA CMOS floating-gate analog voltage reference

A floating gate with stored charge technique has been used to implement a precision voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate analog voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.     

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

A new compact temperature-compensated CMOS current reference

This paper describes a new circuit integrated on silicon, which generates temperature-independent bias currents. Such a circuit is firstly employed to obtain a current reference with first-order temperature compensation, then it is modified to obtain second-order temperature compensation. The operation principle of the new circuits is described and the relationships between design and technology process parameters are derived. These circuits have been designed by a 0.35 /spl mu/m BiCMOS technology process and the thermal drift of the reference current has been evaluated by computer simulations. They show good thermal performance and in particular, the new second-order temperature-compensated current reference has a mean temperature drift of only 28 ppm//spl deg/C in the temperature range between -30/spl deg/C and 100/spl deg/C.     

A temperature- and process-tolerant 64K EEPROM

A 64K EEPROM is described with emphasis on the circuit techniques used to achieve extended temperature operation. The core architecture is considered and a suitable byte layout which eliminates possible punchthrough in the memory cell is shown. A feedback-controlled substrate bias generator is described which delivers -1.0 V/spl plusmn/0.05 V and reduces significantly field transistor leakages. In addition, a /spl plusmn/1% stable voltage reference is shown to accurately control the programming voltage for the memory array to 20 V/spl plusmn/1 V over the full military temperature range (-55/spl deg/-+125/spl deg/C) and /spl plusmn/10% power-supply variation. A process-insensitive write timing pulse trimmed by E2 fuses is discussed, as is the PAGE-MODE WRITE circuitry in relation to the bitline latches.     

Low voltage techniques [for micropower operational amplifiers]

A micropower operational amplifier is described that will operate from a total supply voltage of 1.1 V. The complementary class-B output can swing within 10 mV of the supplies or deliver /spl plusmn/20 mA with 0.4 V saturation. Common mode range includes V/SUP -/, facilitating single-supply operation. Otherwise, DC performance compares favourably with that of the LM108. An adjustable-output voltage reference is also presented that uses a new technique to eliminate the bow usually found in the temperature characteristics of the band-gap reference. Minimum supply is 1 V, and typical drift is 0.002 percent//spl deg/C.     

New techniques for drift compensation in integrated differential amplifiers

A technique is described for achieving low-voltage offset and thermal drift in a monolithic integrated differential amplifier. First order compensation is achieved, under severe restrictions, for a simple differential pair. An alternative balancing technique utilizes the linear combination of two equal and opposite drift characteristics to minimize drift from all sources. Drift values of /spl plusmn/0.12 /spl mu/V//spl deg/C over the temperature range 0 to 100/spl deg/C have been obtained.     

A monolithic 14 bit A/D converter

A 14 bit monolithic successive approximation A/D converter with 7 /spl mu/s conversion time is described. A special system called `dynamic element matching' is used to construct the high-accuracy D/A converter needed in the system. The high linearity of the converter (/spl plusmn//SUP 1///SUB 4/ LSB) results in an 84 dB S/N ratio. The high-speed comparator consists of a wide-band (75 MHz) clamped operational amplifier followed by a strobed flip-flop to freeze the output data. In the digital part, current mode logic (CML) is used for speed and low interference generation with respect to the analog circuitry. Digital input and outputs are TTL compatible. A low-noise, high-stability reference source with a temperature dependence of /spl plusmn/0.5 ppm//spl deg/C over -20 to +85/spl deg/C completes the A/D function. The chip is processed in a standard bipolar process using double layer interconnection. The die size is 3.5/spl times/4.4 mm/SUP 2/.     

A high-frequency temperature-stable monolithic VCO

A new high-frequency monolithic voltage-controlled oscillator (VCO) is described that achieves /spl plusmn/60 ppm//spl deg/C temperature coefficient of frequency over 0-75/spl deg/C at center frequencies from DC to 20 MHz. The circuit also exhibits good linearity of voltage to frequency, and excellent triangle output waveform over the whole frequency range from low frequencies to 20 MHz. The circuit is fabricated using an eight mask IC process and has a die size of 65/spl times/50 mils/SUP 2/.     

Current regulators for I/SUP 2/L circuits to be operated from low-voltage power supplies

A new bandgap current reference is described which can be used to control the injector current of I/SUP 2/L circuits for supply voltages down to about 1 V. For small currents the total injector current is obtained as a mirror of the reference current. For large injector currents the current control is performed by a series regulator which compares the injector current of one I/SUP 2/L gate to the reference current. The described reference current can be adjusted to give a variation with temperature of about 60 ppm//spl deg/C over the temperature range -10 to +70/spl deg/C. However, in some applications a nonzero, but well controlled temperature coefficient is desired. It is shown how a temperature stable ring oscillator with I/SUP 2/L gates can be constructed by tailoring the temperature dependence of the supply current appropriately.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.