High performance field-effect transistors fabricated with laterally grown ZnO nanorods in solution

We have exploited a method for the lateral growth of multiple ZnO nanorods between electrodes in solution without the use of a metal catalyst to fabricate high performance field-effect transistors (FETs). This method enables us to directly align overlapped or overlap-free nanowires between electrodes by eliminating the vertical growth components and complex structural networks. The overlap-free ZnO nanorod FETs showed better performance with a mobility of ～ 8.5 cm(2) V( - 1) s( - 1) and an on/off ratio of ～ 4 × 10(5) than the overlapped ZnO nanorod FETs having a mobility of ～ 5.3 cm(2) V( - 1) s( - 1) and an on/off ratio of ～ 3 × 10(4). All the FETs fabricated in this work showed much better performance than the previously reported solution-based ZnO FETs.     

NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors with high-k Al(2)O(3) gate layers

Electrical characteristics of NOT and NAND logic circuits fabricated using top-gate ZnO nanowire field-effect transistors (FETs) with high-k?Al(2)O(3) gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whose I(on)/I(off) ratios were as high as ～10(8) were connected in series in a single ZnO nanowire channel, sharing a common source electrode. Its voltage transfer characteristics exhibited an inverting operation and its logic swing was?98%. In addition, the characteristics of a NAND logic circuit composed of three top-gate FETs connected in series in a single nanowire channel are discussed in this paper.     

Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al(2)O(3) gate oxides

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al(2)O(3) tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8?V was observed in its drain current versus gate voltage (I(DS)-V(GS)) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.     

Experimental study on the subthreshold swing of silicon nanowire transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.     

Fully transparent thin-film transistor devices based on SnO2 nanowires

We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.     

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.     

Quantum confinement induced performance enhancement in sub-5-nm lithographic Si nanowire transistors

We demonstrate lithographically fabricated Si nanowire field effect transistors (FETs) with long Si nanowires of tiny cross sectional size (～3-5 nm) exhibiting high performance without employing complementarily doped junctions or high channel doping. These nanowire FETs show high peak hole mobility (as high as over 1200 cm(2)/(V s)), current density, and drive current as well as low drain leakage current and high on/off ratio. Comparison of nanowire FETs with nanobelt FETs shows enhanced performance is a result of significant quantum confinement in these 3-5 nm wires. This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.     

Tunable electronic transport characteristics of surface-architecture-controlled ZnO nanowire field effect transistors

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts. The ZnO nanowires that were grown showed two different types of geometric properties: corrugated ZnO nanowires having a relatively smaller diameter and a strong deep-level emission photoluminescence (PL) peak and smooth ZnO nanowires having a relatively larger diameter and a weak deep-level emission PL peak. The surface morphology and size-dependent tunable electronic transport properties of the ZnO nanowires were characterized using a nanowire field effect transistor (FET) device structure. The FETs made from smooth ZnO nanowires with a larger diameter exhibited negative threshold voltages, indicating n-channel depletion-mode behavior, whereas those made from corrugated ZnO nanowires with a smaller diameter had positive threshold voltages, indicating n-channel enhancement-mode behavior.     

Parallel core-shell metal-dielectric-semiconductor germanium nanowires for high-current surround-gate field-effect transistors

Core-shell germanium nanowires (GeNW) are formed with a single-crystalline Ge core and concentric shells of nitride and silicon passivation layer by chemical vapor deposition (CVD), an Al2O3 gate dielectric layer by atomic layer deposition (ALD), and an Al metal surround-gate (SG) shell by isotropic magnetron sputter deposition. Surround-gate nanowire field-effect transistors (FETs) are then constructed using a novel self-aligned fabrication approach. Individual SG GeNW FETs show improved switching over GeNW FETs with planar gate stacks owing to improved electrostatics. FET devices comprised of multiple quasi-aligned SG GeNWs in parallel are also constructed. Collectively, tens of SG GeNWs afford on-currents exceeding 0.1 mA at low source-drain bias voltages. The self-aligned surround-gate scheme can be generalized to various semiconductor nanowire materials.     

Electrical transport properties of single wall carbon nanotube/polyurethane composite based field effect transistors fabricated by UV-assisted direct-writing technology

We report on the fabrication and transport properties of single-walled carbon nanotube (SWCNT)/polyurethane (PU) nanocomposite microfiber-based field effect transistors (FETs). UV-assisted direct-writing technology was used, and microfibers consisting of cylindrical micro-rods, having different diameters and various SWCNT loads, were fabricated directly onto SiO?/Si substrates in a FET scheme. The room temperature dc electrical conductivities of these microfibers were shown to increase with respect to the SWCNT concentrations in the nanocomposite, and were about ten orders of magnitude higher than that of the pure polyurethane, when the SWCNT load ranged from 0.1 to 2.5 wt% only. Our results show that for SWCNT loads ≤ 1.5 wt%, all the microfibers behave as a FET with p-type transport. The resulting FET exhibited excellent performance, with an I(on)/I(off) ratio of 10? and a maximum on-state current (I(on)) exceeding 70 μA. Correlations between the FET performance, SWCNTs concentration, and the microfiber diameters are also discussed.     

Carbon nanotube multi-channeled field-effect transistors

Field-effect transistors (FETs) with multiple channels of single-wall carbon nanotubes (SWCNTs) have been constructed. SWCNT channels of the FETs are dispersedly aligned between the source and the drain by electric-field manipulation of surface decorated SWCNTs. The obtained multichanneled FETs not only can meet the requirement of large output current and high transconductance, but also manifested good reliability and applicability. It is found that the transconductance of the multi-channel FET has an almost linear dependency on the SWCNT channel number, which opens up a promising way to tune the transconductance of FETs by controlling the channel number.     

The growth and characterization of ZnO/ZnTe core-shell nanowires and the electrical properties of ZnO/ZnTe core-shell nanowire field effect transistor

Vertically aligned ZnO/ZnTe core-shell nanowires were grown on a-plane sapphire substrate by using chemical vapor deposition with gold as catalyst for the growth of ZnO core and then followed by growing ZnTe shell using metal-organic chemical vapor deposition (MOCVD). Transmission electron microscope (TEM) and Raman scattering indicate that the core-shell nanostructures have good crystalline quality. Three-dimensional fluorescence images obtained by using laser scanning confocal microscope demonstrate that the nanowires have good optical properties. The core-shell nanowire was then fabricated into single nanowire field effect transistor by standard e-beam photolithography. Electrical measurements reveals that the p-type ZnO/ZnTe FET device has a turn on voltage of -1.65 V and the hole mobility is 13.3 cm2/V s.     

Ti-doped indium tin oxide thin films for transparent field-effect transistors: control of charge-carrier density and crystalline structure

Indium tin oxide (ITO) films are representative transparent conducting oxide media for organic light-emitting diodes, liquid crystal displays, and solar cell applications. Extending the utility of ITO films from passive electrodes to active channel layers in transparent field-effect transistors (FETs), however, has been largely limited because of the materials' high carrier density (>1 × 10(20) cm(-3)), wide band gap, and polycrystalline structure. Here, we demonstrate that control over the cation composition in ITO-based oxide films via solid doping of titanium (Ti) can optimize the carrier concentration and suppress film crystallization. On 120 nm thick SiO(2)/Mo (200 nm)/glass substrates, transparent n-type FETs prepared with 4 at % Ti-doped ITO films and fabricated via the cosputtering of ITO and TiO(2) exhibited high electron mobilities of 13.4 cm(2) V(-1) s(-1), a low subthreshold gate swing of 0.25 V decade(-1), and a high I(on/)I(off) ratio of >1 × 10(8).     

Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate nanodielectrics

The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.     

Synthesis of Si nanowires with a thermally oxidized shell and effects of the shell on transistor characteristics

Silicon nanowires (SiNWs) with a single-crystalline Si core and a thermally oxidized shell (core-shell SiNWs) were synthesized by gold-catalyzed chemical vapor deposition followed by rapid thermal oxidation. To synthesize high-quality core-shell SiNWs, the relationship between the growth parameters and the crystallinity was studied. Furthermore, the formation process of the oxide shell was analyzed in detail by transmission electron microscopy. Using SiNWs as channels, back gate-type field effect transistors (FETs) were fabricated on p-type silicon wafers. FETs with core-shell SiNWs channels exhibited smaller hysteresis in the drain current (I_d) vs. gate voltage (V_GS) characteristics and higher on/off drain current ratio (I_ON/I_OFF) than those with bare SiNWs channels.     

Sub-100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed

Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si channels by controlled solid-state conversion of Ge/Si NWs to NiSixGe y alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious short-channel effects present in lithographically defined sub-100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drain-source bias of 0.5 V yield transconductance values of 78 and 91 microS, respectively, and maximum on-currents of 121 and 152 microA. The scaled transconductance and on-current values for a gate and bias voltage window of 0.5 V were 6.2 mS/microm and 2.1 mA/microm, respectively, for the 40 nm device and exceed the best reported values for planar Si and NW p-type FETs. In addition, analysis of the intrinsic switching delay shows that terahertz intrinsic operation speed is possible when channel length is reduced to 70 nm and that an intrinsic delay of 0.5 ps is achievable in our 40 nm device. Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub-100 nm Ge/Si NWFETs with integrated high-kappa gate dielectric operate near the ballistic limit.     

InAs/InP radial nanowire heterostructures as high electron mobility devices

Radial core/shell nanowires (NWs) represent an important class of one-dimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantum-confined, high-mobility electron carriers. Transmission electron microscopy studies revealed single-crystal InAs cores with epitaxial InP shells 2-3 nm in thickness, and energy-dispersive X-ray spectroscopy analysis further confirmed the composition of the designed heterostructure. Room-temperature electrical measurements on InAs/InP NW field-effect transistors (NWFETs) showed significant improvement in the on-current and transconductance compared to InAs NWFETs fabricated in parallel, with a room-temperature electron mobility, 11,500 cm(2)/Vs, substantially higher than other synthesized 1D nanostructures. In addition, NWFET devices configured with integral high dielectric constant gate oxide and top-gate structure yielded scaled on-currents up to 3.2 mA/microm, which are larger than values reported for other n-channel FETs. The design and realization of high electron mobility InAs/InP NWs extends our toolbox of nanoscale building blocks and opens up opportunities for fundamental and applied studies of quantum coherent transport and high-speed, low-power nanoelectronic circuits.     

Dopant-free GaN/AlN/AlGaN radial nanowire heterostructures as high electron mobility transistors

We report the rational synthesis of dopant-free GaN/AlN/AlGaN radial nanowire heterostructures and their implementation as high electron mobility transistors (HEMTs). The radial nanowire heterostructures were prepared by sequential shell growth immediately following nanowire elongation using metal-organic chemical vapor deposition (MOCVD). Transmission electron microscopy (TEM) studies reveal that the GaN/AlN/AlGaN radial nanowire heterostructures are dislocation-free single crystals. In addition, the thicknesses and compositions of the individual AlN and AlGaN shells were unambiguously identified using cross-sectional high-angle annular darkfield scanning transmission electron microscopy (HAADF-STEM). Transport measurements carried out on GaN/AlN/AlGaN and GaN nanowires prepared using similar conditions demonstrate the existence of electron gas in the undoped GaN/AlN/AlGaN nanowire heterostructures and also yield an intrinsic electron mobility of 3100 cm(2)/Vs and 21,000 cm(2)/Vs at room temperature and 5 K, respectively, for the heterostructure. Field-effect transistors fabricated with ZrO(2) dielectrics and metal top gates showed excellent gate coupling with near ideal subthreshold slopes of 68 mV/dec, an on/off current ratio of 10(7), and scaled on-current and transconductance values of 500 mA/mm and 420 mS/mm. The ability to control synthetically the electronic properties of nanowires using band structure design in III-nitride radial nanowire heterostructures opens up new opportunities for nanoelectronics and provides a new platform to study the physics of low-dimensional electron gases.     

Simulation, fabrication and characterization of ZnO based thin film transistors grown by radio frequency magnetron sputtering

We report the performance of the thin film transistors (TFTs) using ZnO as an active channel layer grown by radio frequency (RF) magnetron sputtering technique. The bottom gate type TFT, consists of a conventional thermally grown SiO2 as gate insulator onto p-type Si substrates. The X-ray diffraction patterns reveal that the ZnO films are preferentially orientated in the (002) plane, with the c-axis perpendicular to the substrate. A typical ZnO TFT fabricated by this method exhibits saturation field effect mobility of about 0.6134 cm2/V s, an on to off ratio of 102, an off current of 2.0 x 10(-7) A, and a threshold voltage of 3.1 V at room temperature. Simulation of this TFT is also carried out by using the commercial software modeling tool ATLAS from Silvaco-International. The simulated global characteristics of the device were compared and contrasted with those measured experimentally. The experimental results are in fairly good agreement with those obtained from simulation.