基于TMS320VC5410 DMA方式的高速并行采样系统设计

针对便携式图像系统中视频信号采集与数字处理的需求，设计了以TMS320VC5410(DSP)为核心的通用采样处理系统。利用VC5410的6通道DMA(直接内存存取)控制端口，实现了信号的高速并行采样，其采样率最高可达20MBps。介绍了并行采样系统硬件组成、DMA控制端口逻辑关系以及高速并行采样的编程实现。     

Design of a high speed parallel encoder for convolutional codes

This paper presents the design of high speed parallel architectures for convolutional encoders and its implementation on FPGA devices. Convolutional codes are widely used in telecommunication applications to improve the data transmission reliability over noisy chanels.The architecture proposed here combines parallel and pipelining techniques. A purely parallel approach can increase the number of processed bits per clock cycle. Unfortunately, the critical path propagation delay increases with the parallelism level. Consequently, the operating clock frequency decreases which in turn can dramatically limit the benefit of parallelization. This drawback can be significantly reduced using pipelining techniques. As a result, the critical path depends no more on the parallelism level.The encoder architectures have been implemented on FPGA devices of the Altera Flex10KE family. Bit rates up to 6.61 Gbits/s have been achieved on 32-bit parallel implementations.     

基于FPGA的高速数据处理系统设计

针对光纤微扰动传感器的高速数据处理问题,设计一种以XC4VSX25为核心,具有数据采集功能、存储功能、LCD显示功能和USB通信功能的系统。利用XC4VSX25带有的XtremeDSPTM IP核,通过并行运算解决高速实时数据处理问题,并且通过Verilog HDL语言设计串行结构和并行结构,并在ModelSim中对两种结构进行仿真比较。结果表明,本系统中并型结构的计算速度是正比于并行度的,可以提高系统处理速度。     

Simplified modeling of parallel plate resonances on multilayerprinted circuit boards

Multilayer printed circuit boards (PCBs) are currently used in various areas of electronics such as telecommunications. However, high crosstalk between signal vias can cause degradation of performance for these kinds of structures. Resonances of parallel ground or power planes can increase this crosstalk. In this study, a simplified approach to the modeling of these resonances is described. It is assumed that the fields inside the board have characteristically only two-dimensional (2-D) variation. When this hypothesis is valid, it is shown that resonances can be measured on two-layer prototyping boards and simulated using a 2-D finite-difference model. It is additionally noted that a previously suggested method of using coaxial ground vias to suppress coupling between vias is not necessarily effective if there are resonant parallel plates on the board. Agreement between measured and modeled results is good enough for practical design purposes. The main advantages of the method used in this study compared to the more robust three-dimensional (3-D) simulation models are savings in time and costs. Additionally, prototyping is much easier on two than multilayer boards     

Accurate estimation of Doppler shift in mobile communications with high vehicle speed

Representing the channel varying rate and the mobile speed of a mobile terminal directly, Doppler shift is an important parameter in vehicular mobile communications and therefore is widely used in mobile target detection and adaptive applications. Hence, this paper puts forward an accurate Doppler shift estimator in mobile communications with high vehicle speeds, which can also be treated as a vehicular speed estimator due to the well‐known relation between the Doppler shift and the mobile speed. Specifically, the proposed estimator is based on the channel level crossing rate, and an iterative process is presented to achieve signal‐to‐noise ratio (SNR) insensitive estimates in accordance with the level crossing rate estimation error analysis. Moreover, we prove the convergency of the iterative Doppler shift estimator in theory. Computer simulations conducted under a wide range of noise corruption clearly show that the proposed estimator substantially outperforms several existing estimators in terms of accuracy and achieves a good SNR‐insensitive performance in a wide range of velocities and SNRs. Copyright © 2013 John Wiley & Sons, Ltd.     

A high speed,precision voltage buffer in a submicron CMOS process

A new buffer architecture was introduced by Comer and Comer (1998, International Journal of Electronics, 84, 345). This buffer uses an active feedback network based on a transconductance amplifier. An implementation of the new buffer was done in a CMOS process. The buffer was intended for the output stage of a 10-bit video digital-to-analogue converter. The circuit was fabricated on the American Microsystems 0.6 μm process. Design specifications called for a gain accuracy of 0.1%, an offset voltage shift of no more than 1mV over a commonmode input range of 50% of supply voltage and a bandwidth of 500MHz. The actual circuit showed a gain error of less than 0.1%, a common-mode offset variation of less than 2mV, and a bandwidth of 450MHz.     

高速并行总线接口信号的完整性及设计优化

文章主要针对高速并行总线接口信号问题进行研究,首先提出高速并行总线互连设计以及信号完整性相关概念,在此基础上提出引起信号不完整的发射、串扰、同步开关噪声以及码间干扰,针对这些问题提出优化策略。     

Optimized parallel decoding of difference set codes for high speed memories

The interest in using advanced Error Correction Codes (ECCs) to protect memories and caches is growing. This is because as process technology downscales, errors are more frequent and also tend to affect multiple bits. For SRAM memories and caches, latency is a limiting factor and ECCs have to provide low decoding times that can in most cases be only achieved with the use of a parallel decoder. One important issue with parallel decoders is that they typically require large circuit area to be implemented. One type of ECCs that has been explored for memory protection is Difference Set (DS) codes. In this research note, an optimized parallel decoding scheme for DS codes is presented and evaluated. The results show that the circuit area and the decoding delay are reduced compared to a traditional implementation. In addition, the new scheme enables a reduction in the number of parity check bits thus reducing the memory size.     

基于新型介电弹性体平行板电容器的研究

为了研究具有传感功能的可变电容器,采用新型介电弹性体材料制成平行板电容器。研究了该电容器充放电前后的外形变化及影响电容大小的因素。结果表明:在高压充放电前后,电容器的极板面积和两电极板间距离都发生了明显的变化;电容随着外加电压的增大而增大;在外加电压为6 000 V的条件下,电容随着材料预拉伸的增大出现一极大值,随后又减小,即在变化过程中存在拐点;另外,电容器的电极材料用石墨粉时要比用导电胶时电容大。     

Small-signal modeling of a controlled transformer parallel regulator as a multiple output converter high efficient post-regulator

This paper presents a post-regulator based on the use of a controlled transformer, which adds or subtracts an additional voltage to the output filter of a converter in order to regulate its output voltage. So, their actuation is complementary to that of more known post-regulators, such as the magnetic amplifier (magamp) and synchronous switch post-regulator (SSPR), because the regulation is achieved by controlling the voltage across the filter inductor instead of its charge time. Besides, the post-regulator processes the power in parallel to the one flowing from input to output and only handles a percentage of it. The post-regulation by controlled transformer is suitable of being employed in any isolated PWM power converter and combines a good efficiency and the easiness of design of classical switched power supplies. The work describes the post-regulation strategy for obtaining two outputs independently regulated, and presents a model to obtain the control transfer function and the cross-impedance expressions.     

Simple high frequency solution for interior fields of open-ended parallel plate waveguide

The problem of electromagnetic (EM) plane wave scattering by an open-ended, perfectly-conducting, semi-infinite two-dimensional (2-D) parallel plate waveguide with a thin uniform layer of lossy material on its inner walls is analysed using a high frequency method. The fields coupled into the waveguide from the exterior are found via the uniform geometrical theory of diffraction (UTD) ray method.<>     

基于FPGA的高速DMUX设计

介绍了基于Altera公司FPGA的高速DMUX(数据分路器)设计.通过与DMUX专用器件的比较,说明了这种实现方式的优势.     

Flow and pressure field characteristics in the porous block compact modeling of parallel plate heat sinks

Growing complexity has resulted in an increased computational effort in CFD modeling of electronic systems. To reduce the computational effort, one or several heat sinks can be represented by a compact "porous block" model, with an effective thermal conductivity and pressure loss coefficient. In this study of parallel plate heat sinks in laminar forced convection, a methodology is developed to analytically determine the fluid properties of compact heat sink models that provide acceptable levels of approximation. The results of an extensive set of CFD simulations for a three heat sink channel, covering three distinct heat sink geometries, air velocities from 0.25 m/s to 2 m/s and various spacings between the heat sinks, were used to create and evaluate the effectiveness of compact models. Use of a two term, equivalent loss coefficient-reflecting the linear and quadratic components in the pressure drop of a porous block-has led to good agreement between the detailed numerical and compact model predictions, with compact heat sink pressure drops usually slightly higher (<10%) than detailed heat sink pressure drops.     

基于电荷补偿的金属化膜电容器自愈测试方法

利用金属化膜电容器发生自愈时会引起电容极板间电压下降,并使与其并联的储能电容为其充电以补偿电荷这一原理,设计了一种较为简单、有效的自愈测试方法。该方法利用示波器监测自愈发生时储能电容给被测电容的充电电流作用于采样电阻而形成的脉冲电压信号,以该信号的出现作为判断自愈发生的依据,并根据该信号特性计算自愈能量损失。仿真和实验结果证明,该方法能够较为准确地检测到自愈的发生,并计算出自愈造成的能量损失,30个实际测试样本数据显示,采用该方法计算的自愈能量损失与实际自愈能量损失相比,其误差范围在-3.83%~5.71%内,有较高的准确度。     

平行板电容器中介质受力问题的讨论

用虚功原理计算介质块在平行板电容器中的受力,是一道经典电磁场例题。在忽略边缘效应的情况下,垂直方向的电场如何产生了一个横向的作用力？本文回顾和分析了历史上的一些讨论,明确了边缘场对介质中电偶极矩的作用是介质受到横向力的根本原因,解释了为什么使用虚功原理可以忽略边缘效应,讨论了介质分界面的受力问题,澄清了一些错误的认识。     

基于dSPACE的高速高精度并联机器人控制系统设计

并联机器人已被广泛应用于高速运动和高精度定位场合,其控制系统设计也需要根据高速或高精度的应用需要进行针对性设计,以更好发挥机器人的性能。本文基于dSPACE的快速原型技术,设计并构建了平面3-RRR并联机器人的控制系统。针对高速运动、精密定位两种使用目的,设计了三种Simulink控制模型,解决了机器人在位置控制模式与力矩控制模式的驱动问题。试验中一方面完成了机器人的轨迹跟踪,另一方面测量了运动学标定前后定位误差分布,验证了该控制系统应用于高速、高精度控制的可行性。     

基于静电驱动的平行板式微执行器的静态吸合现象的研究

本文先讨论了基于静电驱动的平行板式微执行器在忽略边缘效应下的静态吸合现象,之后在前面研究的基础上,进一步分析了该微执行器在考虑边缘效应下的静态吸合现象,最后建立该微执行器的模型,并设置参数,仿真得到结果证明静态吸合现象的发生.     

基于Cadence软件的高速SDRAM的设计

论述了同步动态SDRAM与高速DSP处理芯片TMS320C6701接口的高速PCB板的设计过程。介绍高速PCB设计的思路和应用Cadence PSD高速PCB设计软件进行板上信号完整性分析的方法,通过对器件的IBIS模型进行仿真,依靠仿真结果指导设计和制作,并经过实际试验,其测试结果与仿真结果基本吻合。系统实现了最佳性能,提高了工作效率,缩短了研发周期。     

JFET's fabricated in a standard IC process for bipolar transistors

A new method for the fabrication of n- and p-channel JFETs in a standard IC process for bipolar transistors is presented. Using special layout techniques, which are based on well-known principles, JFETs of good performance are obtained, provided a tightly controlled photoresist process is available.