RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-$mu{hbox {m}}$ CMOS technology. An operating frequency of 2.5 GHz and phase noise of $-$ 95.4 dBc/Hz at 1$~$MHz offset was measured. Power consumption was 2.86 mW from a 1.3$~$ V supply voltage.      

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 $mu hbox{m}$ digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is $-101~hbox{dBc}/hbox{Hz}$ @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 $~$GHz clock while consuming 14 mW in 90 nm CMOS.      

CMOS ring VCO for UHF RFID readers

A complementary metal oxide semiconductor (CMOS) voltage controlled ring oscillator for ultra high frequency (UHF) radio frequency identification (RFID) readers has been realized and characterized. Fabricated in charter 0.35 μm CMOS process, the total chip size is 0.47×0.67 mm2. While excluding the pads, the core area is only 0.15×0.2 mm2. At a supply voltage of 3.3 V, the measured power consumption is 66 mW including the output buffer for 50 Ω testing load. This proposed voltage-controlled ring oscillator exhibits a low phase noise of - 116 dBc/Hz at 10 MHz offset from the center frequency of 922.5 MHz and a lower tuning gain through the use of coarse/fine frequency control.     

A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning

A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13- $mu$m CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of $-$103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.      

Low Phase-Noise Planar Oscillators Employing Elliptic-Response Bandpass Filters

In this paper, a low phase-noise planar oscillator employing an elliptic bandpass filter as a frequency stabilization element within its feedback loop is presented. The oscillator phase noise is significantly reduced by taking advantage of the group-delay peaks formed at the passband edges of the elliptic filter. A filter optimization technique for low phase-noise oscillator designs is introduced and applied to a four-pole bandpass elliptic filter. An $X$-band oscillator using the optimized filter in the feedback loop is designed and tested. At the oscillation frequency of 8.05 GHz, the measured phase noise is $-$143.5 dBc/Hz at 1-MHz offset frequency. The oscillator exhibits an output power of 3.5 dBm with an dc–RF efficiency of 10%. To the authors' best knowledge, this is the lowest phase noise performance for an $X$-band planar microwave oscillator.      

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.     

A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 $~muhbox{m}$ CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of $-hbox{116~dBc/Hz}$ at 1 MHz offset from a 2.55$~$GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of $-hbox{122.8~dBc/Hz}$ at 1$~$ MHz offset from a 4.77 GHz carrier.      

Low Noise Wide Tuning Range Quadrature Ring Oscillator for Multi-Standard Transceiver

This letter presents a low phase noise quadrature ring oscillator with new start-up circuit. The oscillator architecture is a two-stage differential ring with an additional pair of transition-assistance transistors. The circuit was implemented in 0.18 $mu{rm m}$ CMOS technology and the measured tuning range of the prototype device is from 1.7 GHz to 5.5 GHz and figure of merit (FOM) is ${- 162}~{rm dB}$. The proposed area of application is the core of the local oscillator in a multi-standard wireless transceiver.      

A Low-Noise Wide-BW 3.6-GHz Digital $DeltaSigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancellation to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-$mu$m CMOS process, the prototype occupies 0.95-mm$^{2}$ active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is $-$108 and $-$150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

一种三阶环形压控振荡器的分析设计

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator(ring VCO)based on a different cascade voltage logic delay cell with current-source load to change the current of output node.The method for optimization is presented.Furthermore,the analysis of performance of the proposed ring VCO is confirmed by the measurement results.The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC.The measurement results show that the oscillator frequency of the ring VCO is from 0.770 to5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of15.1 mW from a 1.8 V supply while occupying only 0.00175 mm2of the core die area.     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

A Novel Broad-Band MMIC VCO Using an Active Inductor

This paper proposes a novel broad-band MMIC VCO using an active inductor. This VCO is composed of a serial resonant circuit, in which the capacitor is in series with an active inductor that has a constant negative resistance. Since the inductance value of this active inductor is inversely proportional to the square of the transconductance and can vary widely with the FETs gate bias control, a broad-band oscillation tuning range can be obtained. Furthermore, since this active inductor can generate a constant negative resistance of more than 50 , the proposed VCO can oscillate against a 50- output load immediately without using additional impedance transformers. We have fabricated the VCO using a GaAs MESFET process. A frequency tuning range of more than 50%, from 1.56 to 2.85 GHz, with an output power of 4.4±1.0 dBm, was obtained. With a carrier of 2.07 GHz, the phase noise at 1-MHz offset was less than –110 dBc/Hz. The chip size was less than 0.61 mm², and the power consumption was 80 mW. This broad-band analog design can be used at microwave frequencies in PLL applications as a compact alternative to other types of oscillator circuits.     

用于以太网物理层时钟同步PLL的VCO设计

研究了一种基于以太网物理层时钟同步的高带宽低噪声压控振荡器（VCO）,该VCO采用交叉耦合的电流饥饿型环形振荡器,通过级联11级环路电路和改善其控制电压变换电路,优化了VCO的输出频率范围以及降低了输出时钟的相位噪声,完全满足以太网物理层芯片时钟电路的性能指标。基于TSMC3．3V0．25μmCMOS工艺的仿真结果表明,中心频率为250MHz时,压控增益为300MHz／V,其线性区覆盖范围是60～480MHz,在偏离中心频率600kHz处的相位噪声为-108dBc。     

Investigation of a high frequency CMOS unsaturated ring oscillator

Investigation of a high frequency unsaturated ring oscillator with cross coupled load is presented, and oscillation frequency compared with multi-path high frequency ring oscillators. Stability of oscillation is shown heuristically, via geometric argument on a phase plane, where the presence of negative impedance in the cross coupled pair of the delay cell is deemed important. Oscillation frequency formula is presented, and design insight given. In addition, a novel design methodology on lowering its phase noise is developed. Simulations on example circuit designs using 0.18???m CMOS technology demonstrate the higher frequency obtained, oscillation stability, frequency formula and design insight, as well as phase noise methodology.     

A 22-GHz push-push CMOS oscillator using micromachined inductors

This letter presents a low phase noise 0.35-/spl mu/m CMOS push-push oscillator utilizing micromachined inductors. This oscillator results in an improvement in phase noise compared with the previously published Si-based voltage-controlled oscillators (VCOs) around 20GHz. With the high-Q inductors introduced by the micromachined structure, the oscillator achieves an oscillating frequency of 22.2GHz while exhibiting an output power of -7.5dBm with a phase noise of -110.1dBc/Hz at 1-MHz offset. This work also demonstrates the highest operating frequency among previously published Si-based VCOs using micromachined structures.     

Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

The voltage-controlled oscillator (VCO) in frequency-based $\Updelta\Upsigma$ modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving ?125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670???W at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the $\Updelta\Upsigma$ modulator.     

A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.      

A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique

A 0.18 $mu$ m CMOS quadrature voltage-controlled oscillator with an extremely-low phase noise is presented. The excellent phase noise performance is accomplished by integration of the back-gate quadrature phase coupling and source resistive degeneration techniques into a complementary oscillator topology. The measured phase noise is as low as ${-}133$ dBc/Hz at 1 MHz offset from 3.01 GHz. The output phase imbalance is less than 1$^{circ}$ . The output power is $-1.25{pm} 0.5$ dBm and harmonic suppression is greater than 30.8 dBc. The oscillator core consumes 5.38 mA from a 1.5 V power supply. This QVCO achieves the highest figure-of-merit of ${-}193.5$ dBc/Hz.