应用于神经信号再生系统的跨导放大器

采用华润上华0.6μm标准CMOS混合信号工艺设计了一种应用于植入式神经信号再生系统的跨导放大器.该放大器采用全差分结构以获得高输出摆幅,利用源反馈技术改善线性度,并设计了共模反馈电路以稳定共模输出电压.该跨导放大器工作在5V的电源电压下,具有0.55 S的跨导增益和100 kHz的3 dB带宽,可以满足系统的需要.     

采用单运算跨导放大器的混合模式滤波器

提出了一种新颖的单运算跨导放大器的混合模式滤波器电路。由该电路可实现一阶低通,一阶高通,二阶低通及二阶带通滤波器,所有滤波器仅由一个ＯＴＡ及３－４个ＲＣ元件构成。分析了各种滤波器的灵敏度,并给出了实验结果。     

宽带运算跨导放大器OPA660

介绍了Ｂｕｒｒ－Ｂｒｏｗｎ公司生产的宽带运算跨导放大器ＯＰＡ６６０的特性和工作原理,分析了它的三种基本组态以及与三极管电路的异同,对使用中的具体问题作了说明,并介绍了二个典型的应用电路。     

CMOS浮地电源交叉耦合运算跨导放大器

提出了一种高线性度运算跨导放大器．该电路采用ＣＭＯＳ对管和浮地电源交叉耦合作输入级。对所描述的电路进行了理论分析和计算机模拟．结果表明，在传输特性的非线性误差不大于１％时，电路的差动输入电压范围可达±２．８Ｖ。     

一种3 V CMOS恒跨导运算放大器的设计

提出了一种适合在3V电源电压下工作的CMOS运算放大器，其动态工作范围为0-3V，在整个工作范围内，运算放大器的跨导基本保持不变，给出了BSIM3V3模型下的Hspice模拟结果。     

一种高增益的CMOS差分跨导放大器

本文设计了一种可用于∑△A/D转换器的全差分跨导放大器（OTA）。本放大器采用0.6μm工艺实现，其两级间使用共源共栅补偿、并采用了动态共模反馈，其标定动态范围（DR）为82.8dB、开环直流增益为90.9dB，在最坏情况下需要84.3ns以稳定到0.1%的精度。     

应用于包络跟踪的高线性跨导运算放大器的设计

设计了一款改进的基于交叉耦合结构的跨导运算放大器(OTA)。设计和分析过程中依据严格的理论推导,新结构在高输入摆幅下线性度得到明显优化,当输入为2V@5MHz正弦波时,谐波总量从0.7%降至0.3%,并成功应用于包络跟踪功率放大器。仿真测试基于CSMC 0.5μm CMOS工艺,仿真结果表明二到五次谐波分量总和从传统OTA的-40 dB降低到-52 dB,同时在VSS系统联合仿真平台上,用15 MHz带宽的OFDM调制信号测试星座图,其聚敛性也得到了明显优化,矢量误差从4.7%降至3.6%。     

跨导型运算放大器NE5517应用

<正> 我们通常见到的运算放大器电路,都是围绕电压输入一电压输出的常规型运放而设计的。而另一种类型的运放也常用于很多音频处理场合中,它采用电压输入→电流输出(跨导)形式工作,增益由外接控制端控制,这种器件称作跨导型运算放大器(OTA),NE5517就是一款这样的集成电路。图1为 OTA 的电路符号和工作时     

一种0.18μm CMOS低电压低功耗跨导运算放大器

采用TSMC 0.18μm CMOS工艺,设计了一种低电压、低功耗跨导运算放大器。基于BSIM3V3.1Spice模型,采用Hspice对整个电路进行仿真。在±0.75V电源电压下,电路的直流开环增益达到83dB,相位裕度为63°,功耗为14μW。采用一种应用于低电源电压、低功耗的基准电路,不仅可为运放提供稳定的偏置电流,而且进一步降低了电路的总体功耗。     

一种高增益带宽积CMOS跨导运算放大器

提出了一种高增益带宽积CMOS跨导运算放大器,它采用多级前馈补偿结构。该跨导运算放大器采用调零电阻补偿技术,取消了一个非主极点,以提高电路的增益带宽积。电路采用0.18 μm 标准CMOS工艺进行设计,并采用Hspice工具仿真。仿真结果表明,在1.2 V工作电压下,直流增益为71 dB,增益带宽积为1.4 GHz,功耗为2.2 mW。     

轨到轨输入输出范围运算放大器的噪声分析和优化

这篇文章设计了一个轨到轨（Rail-to-Rail）输入输出范围的低噪声运算放大器,在输入级采用电流补偿的方法来稳定该运算放大器在整个输入共模范围内的跨导,在输出级使用了AB类的输出方法来提高运算放大器的输出范围,且详细分析了该运算放大器的噪声性能,在此基础上给出了改善该运算放大器噪声性能的方法,以此来提高该运算放大器的动态范围。     

A wideband integrated circuit amplifier for fixed-gain application

Circuits which achieve precise gains without the use of negative feedback are of interest because of their simplicity and potential for achieving large bandwidths. A circuit architecture based upon precision current mirrors for producing fixed gains without the use of feedback has been reported in the literature and implemented on a BiCMOS process [1]. This paper provides further analysis of this approach and applies it to a new bipolar amplifier, intended for such applications as real-time active filter synthesis.     

High-performance current differencing transconductance amplifier and its application in precision current-mode rectification

A CMOS-based circuit for realization of high-performance current differencing transconductance amplifier (CDTA) is demonstrated. The proposed circuit offers the advantages of a wide frequency bandwidth and very small input terminal impedance. The results of circuit simulations and an application example are given to illustrate the advantages of the proposed circuit for precise high-frequency signal rectification.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

一种输入输出轨到轨的电流模式仪表放大器设计

本文提出了一种基于标准CMOS工艺的电流模式仪表放大器.该放大器内部运放采用斩波调制技术去除低频1/f噪声和失调,并采用正、负电荷泵,使系统具有轨到轨的输入能力.芯片使用TSMC 0.25μm CMOS混合信号工艺模型设计并流片.测试结果表明,使用60kHz的斩波频率,系统增益为40dB时,具有100dB的共模抑制比和...     

A new OTA-C current-mode biquad filter with single input and multiple outputs

A new current-mode biquad-filtering circuit with single input and multi-outputs based on operational transconductance amplifier (OTA) is presented using three OTAs, two grounded capacitors and one grounded resistor, it can simultaneously realize second-order lowpass, bandpass, highpass, notch and allpass filters. The characteristic parameters can be adjusted orthogonally by a bias current of OTA and all capacitors are gounded. Morever, the circuit enjoys low sensitivities.     

A high speed low input impedance current pulse amplifier cell

A high speed CMOS current pulse amplifier cell with low input impedance, devoted to nuclear multichannel detectors where crosstalk is a serious problem, is presented. The symmetry of the circuit achieved with complementary transistors yields both an input and an output with low offset voltage, opening a large field of applications such as transimpedance amplifiers and therefore transimpedance operational amplifiers.     

一种应用于PWM D类音频功率放大器的CMOS Rail-to-Rail比较器

提出了一种应用于CMOS D类音频功率放大器的Rail-to-Rail PWM比较器,其输入级为Rail-to-Rail结构,输出级为AB类输出。基于CSMC 0.5μm CMOS工艺的BSIM3V3 Spice模型,采用Hspice对PWM比较器的特性进行了仿真,典型模型下的直流开环增益为50dB,电源抑制比为52dB,ICMR为0.04V~4.98V,传输时延为24.5ns,版图有效面积为210×75μm2。由于PWM比较器的良好性能参数,所以其不仅适用于D类音频功率放大器,也能应用于各类低频数据转换电路。     

Low leakage and high CMRR CMOS differential amplifier for biomedical application

In order to increase user experience in using near field communication smartcard, analog front-end (AFE) module is required to provide a sufficient and a well-regulated voltage regardless the distance between the card and the reader. A highly stable AFE design for energy harvesting purpose is introduced in this paper. The design consists of antenna, rectifier, voltage limiter, bandgap reference, and low-dropout (LDO) voltage regulator circuit. The antenna is designed to resonate at 13.56 MHz as regulated by ISO/IEC 14443-2. In order to simplify the implementation using 0.18 μm CMOS process, a full-wave rectifier circuit is built of all low-threshold-voltage diode-connected PMOS transistors. To protect the system from undesired excessive input voltages, a voltage limiter circuit is included in the module. Moreover, control and maintain a stable supply voltage for the whole system, a robust LDO voltage regulator and bandgap circuits are specially designed for this purpose. The LDO is able to provide a stable 1.8 V of supply voltage with a sub-1% ripple factor even under a low input current as low as 20 mA.     

CMOS毫米波低功耗超宽带共栅低噪声放大器

陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA).该LNA用标准90-nm RFCMOS工艺实现并具有如下特征:在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2dB,平均NF在27 ～ 42 GHz频段内为5.1 dB;S11在整个测试频段内小于-11 dB.40 GHz处输入三阶交调点(IIP3)的测试值为+2 dBm.整个电路的直流功耗为5.3 mW.包括焊盘在内的芯片面积为0.58 mm×0.48 mm.