Performance analysis of RF MEMS capacitive switch with non uniform meandering technique

This Paper reports on investigation of High C_on C_off ratio Capacitive Shunt RF MEMS Switch and detailed comparison between uniform three meander beam with non-uniform single meander beam RF MEMS switch. RF MEMS Switches are designed for operation in the range 5–40 GHz. Pull in analysis is performed with gold as a beam material. Simulation reveals that use of high K dielectric material can drastically improve the capacitance ratio of switch. For the same geometry, pull in voltage is 2.45 V for HfO₂, 2.7 V for Si₃N₄ and Capacitive Ratio of the switch with Si₃N₄ is 83.75 and Capacitive Ratio with HfO₂ is 223 at 2g₀ (air gap) and 0.8 μm thickness of beam. The Radio Frequency performance of RF MEMS switch is obtained by scattering parameters (insertion loss, Return loss and isolation) which are mainly dominated by down to up capacitance ratio and MEMS bridge geometries. RF analysis shows that insertion loss as low as ?0.4 dB at 20 GHz and isolation as high as 80 dB at 20 GHz can be achieved. Investigation of three uniform meander Design and non-uniform single meander design reveals that use of non-uniform design reduces the design complexity and saves substrate area still maintaining almost same device performance. S-parameter analysis is carried out to compare device performance for both structures. DC analysis of the proposed switch is carried out using Coventorware and RF analysis is performed in MATLAB.     

A simplification method for capacitance models in AlGaN/GaN high electron mobility transistors under large drain voltage using channel analysis

This article analyzes the bias dependence of gate‐drain capacitance (C_gd) and gate‐source capacitance (C_gs) in the AlGaN/GaN high electron mobility transistors under a high drain‐to‐source voltage (V_ds) from the perspective of channel shape variation, and further simplifies C_gd and C_gs to be gate‐to‐source voltage (V_gs) dependent only at high V_ds. This method can significantly reduce the number of parameters to be fitted in C_gd and C_gs and therefore lower the difficulty of model development. The Angelov capacitance models are chosen for verifying the effectiveness of simplification. Good agreement between simulated and measured small‐signal S‐parameters, large‐signal power sweep, and power contours comprehensively proves the accuracy of this simplification method.     

The beneficial impact of a p–p+ junction on DC and analog/radio frequency performance of a vertical super-thin body FET

This article investigates the impact of the p–p⁺ junction (at the body-substrate interface) on different direct current (DC) and analog/radio frequency (RF) performance parameters of a newly invented structure called vertical super-thin body field effect transistor (VSTB FET) through a well-calibrated TCAD tool. At a fixed body doping, the influence of p–p⁺ junction was inspected for different substrate doping (N_s); which reveals that N_s has a robust control on the device electrostatics. Interestingly, higher N_s is seen to significantly suppress different short channel effects (SCEs), which in turn helps to improve various DC parameters excellently. An increase in N_s from 10¹⁵ to 10¹⁸ cm^?3 improves off-state leakage current and on-to-off current ratio by three orders of magnitude. Also, such a change in N_s decreases subthreshold swing and drain-induced-barrier-lowering by 8.78 mV/dec and 11.15 mV/V, respectively. The underlying physics behind such improvement at higher N_s is explored through the off-state channel electron density profiles corresponding to different N_s values. Further, different analog/RF parameters such as transconductance, input capacitance, gate-drain capacitance, output conductance, gain-bandwidth-product, and transconductance frequency product (TFP) show slight improvement for increasing N_s. In contrast, TGF, GFP, and GTFP offer large enhancement at higher N_s. This study is expected to demonstrate the significance of N_s on device performance.     

Influence of dielectric material near tunnel junction on analog/RF and linearity figure of merits in hetero dielectric (HG) TFET: A detailed study

In this work, the effect of dielectric material near the source region on analog/RF and linearity figure of merits in hetero gate TFET (HG-TFET) are investigated through Technology Computer Aided Design device simulator. The various dielectric materials considered in this study are SiO₂, Al₂O₃, and HfO₂. The several RF/analog metrics studied in this work are transconductance (g_m), output conductance (g_d), gain (g_m/g_d), gate capacitance, cut-off frequency, and gain frequency product. Furthermore, the various linearity parameters discussed are higher order derivative of g_m (g_m2 and g_m3), voltage intercept points (VIP2 and VIP3), 3rd-order input intercept power, and 3rd-order intermodulation power for different high-k dielectric near the source region in HG-TFET. Results reveal that RF/analog performance is improved, whereas, the linearity characteristic is suppressed in HG-TFET using HfO₂ as the gate dielectric near the source.     

Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET

In this present work, we explore the hot carrier fidelity of gate electrode workfunction engineered silicon nanowire (GEWE-SiNW) MOSFET at 300 K using DEVEDIT-3D device editor and ATLAS device simulation software. TCAD simulation shows reduction in the hot carrier reliability of a GEWE SiNW MOSFET in terms of electron temperature, electron velocity and Hot Electron gate current for reflecting its efficacy in high power CMOS applications. Further, a comparative investigation for different values of oxide thickness and high-k has been done to analyze the performance of GEWE-SiNW MOSFET in terms of electrical parameters such as conduction band, DIBL, electric field, electron temperature, electric velocity and gate current. It has been clearly shown that with oxide thickness 0.5 nm the hot-carrier reliability and device performance improves in comparison to oxide thickness 2.5 nm. In addition, with k = 21(HfO₂) device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in sub-nm range analog applications.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis

This work explores the temperature associated reliability issues of selective buried oxide (SELBOX) TFET. The proposed device is optimized for maximum I_ON/I_OFF ratio considering various gap positions in the buried oxide. The variation of DC parameters such as I_D‐V_GS characteristics, subthreshold swing (SS) and I_ON/I_OFF ratio for a wide range of temperature from 300 K to 500 K has been studied. The proposed SELBOX device is compared with conventional silicon‐on‐insulator device considering various RF parameters. Moreover, the dependency of RF performance of the proposed device on temperature has been examined. The variation of RF parameters such as transconductance (g_m), cut‐off frequency (f_T), gate capacitance (C_GG), intrinsic delay and transconductance frequency product (TFP) with temperature has also been studied. The linearity of the device has been explored by analyzing the influence of temperature variation on 1‐dB compression point. Further, temperature dependency in the presence of quantum correction (QC) model has been analyzed.     

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors with wet‐etched electrodes

Process development of inverted‐staggered amorphous InGaZnO thin‐film transistors (a‐IGZO TFTs) with wet‐etched electrodes was employed in this paper. Five metals (Al, Cu, Ti, Ta, and Cr) as well as various etchants were comparatively investigated, indicating H₂O₂ based solution etched Ta films were good candidates for the wet‐etched electrodes of a‐IGZO TFTs. The aforementioned findings along with other improving attempts successfully established inexpensive processing steps and conditions with which stable a‐IGZO TFTs were finally fabricated. The device performance was reasonably good enough (μ_FE of 6.0 cm²/V·s, V_th of 2.5 V, SS of 1.8 V/decade, and I_on/I_off of 10⁶) to meet the requirements of applications especially for small‐sized flat panel displays.     

Cyclic bundle Hamiltonicity

Cyclic bundle Hamiltonicity cbH(G) of a graph G is the minimal n for which there is an automorphism α of G such that the graph bundle C _n □^α G is Hamiltonian. We define an invariant I that is related to the maximal vertex degree of spanning trees suitably involving the symmetries of G and prove cbH(G)≤I≤cbH(G)+1 for any non-trivial connected graph G.     

pH-ChemFET-based analysis devices for the bacterial activity monitoring

Silicon and polymer microtechnologies have been developed in order to integrate pH-metry techniques in the frame of medical diagnosis. Thus, a fluidic analysis device has been designed and realised in order to monitor pH-related bacterial activities. It includes a SiO₂/Si₃N₄ pH-sensitive chemical field effect transistor (pH-ChemFET), its titanium/gold pseudo-reference gate electrode and a poly-dimethylsiloxane (PDMS) integrated flow-cell (total volume: ≤2 mm³). The whole analysis device has been used to detect the biological activities of the Lactobacillus crispatus bacteria and to estimate its sensitivity to antibiotics. Results demonstrate the detection of pH-related bacterial metabolisms in microvolumes, enabling to reduce significantly the analysis response time with regards to standard procedures and to the development of pH-ChemFET-metry for medical analysis.     

Simulation of time-dependent effects of pH-ISFETs

It has been shown that the accuracy of ISFETs is limited by the time-dependent effects which include slow response and drift. The abnormal phenomenon will result in hysteresis. The time-dependent effects of the device can be modeled by mathematical expression. In this paper, we use multi-exponential step-response expression to fit the previous experimental data of total response of various gate insulator such as Ta₂O₅, Si₃N₄ and a-Si:H. The curve-fitting employ the method of least squares criteria to extract the time constant and amplitude. The extracted parameters were used to simulate the mechanism of hysteresis. The previous data of pH-response of a-Si:H in our laboratory can be combined with earlier measurements of Ta₂O₅, Si₃N₄ surfaces to simulate their hysteresis property at a loop time of 160 min (9600 s). The magnitude of normalized hysteresis width of simulation was found: a-Si:H>Si₃N₄>Ta₂O₅.     

Characterisation of silicon carbide JFETs with respect to microsystems for high temperature applications

 In this work first commercially available SiC-transistor prototypes were tested with regard to their applicability in high temperature electronic circuits for sensor signal conditioning. The influence of the temperature on the device behaviour (drain-saturation current, gate leakage current, I–V-characteristics, long-term effects) was investigated. The devices showed reliable operation up to 450 °C. The maximum forward transconductance g _m and the short circuit drain source current I _DSS decreased to approximately 30% of the room temperature values. Also, a slight increase of the pinch-off voltage V _p was observed. The gate leakage current I _GSS rose with temperature, staying below 1 μA at 450 °C. A pre-ageing study was carried out to verify changes in the device characteristics with time. The devices were exposed to a 270 °C environment and it was observed that the DC parameters tend to stabilise after about 100 h. From the I–V-characteristics the SPICE parameters were extracted for a series of temperatures, allowing the design and optimisation of amplifier gain stages. The SPICE device simulation results are in good agreement with the measured characteristics. Received: 28 November 1996/Accepted: 2 December 1996     

Computing functions on asynchronous anonymous networks

In an “anonymous” network the processors have no identity numbers. We investigate the problem of computing a given functionf on an asynchronous anonymous network in the sense that each processor computesf(I) for any inputI = (I(v ₁),...,I(v _n )), whereI(v _i) is the input to processorv _i ,i = 1, 2,...,n. We address the following three questions: (1) What functions are computable on a given network? (2) Is there a “universal” algorithm which, given any networkG and any functionf computable onG as inputs, computesf onG? (3) How can one find lower bounds on the message complexity of computing various functions on anonymous networks? We give a necessary and sufficient condition for a function to be computable on an asynchronous anonymous network, and present a universal algorithm for computingf(I) on any networkG, which acceptsG andf computable onG, as well as {I(v _i )}, as inputs. The universal algorithm requiresO(mn) messages in the worst case, wheren andm are the numbers of processors and links in the network, respectively. We also propose a method for deriving a lower bound on the number of messages necessary to solve the above problem on asynchronous anonymous networks.     

Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10^?8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (C_G) from 12.04 × 10^?13 to 10.48 × 10^?13 F/mm. Furthermore, the drain current and transconductance (g_m) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut‐off frequency (f_T) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz‐V for 250 nm gate technology without incorporating T‐gate.     

Gain–bandwidth limitations of microwave transistor

This work enables one to obtain the potential gain (G_T) characteristics with the associated source (Z_S) and load (Z_L) termination functions, depending upon the input mismatching (V_i), noise (F), and the device operation parameters, which are the configuration type (CT), bias conditions (V_DS, I_DS), and operation frequency (f). All these functions can straightforwardly provide the following main properties of the device for use in the design of microwave amplifiers with optimum performance: the extremum gain functions (G_{T max}, G_{T min}) and their associated Z_S, Z_L terminations for the V_i and F couple and the CT, V_DS, I_DS, and f operation parameters of the device point by point; all the compatible performance (F, voltage–standing wave ratio V_i, G_T) triplets within the physical limits of the device, which are F ≥ F_min, V_i ≥ 1, G_{T min} ≤ G_T ≤ G_{T max}, together with their Z_S, Z_L termination functions; and the potential operation frequency bandwidth for a selected performance (F, V_i, G_T) triplet. The selected performance triplet and termination functions can be realized together with their potential operation bandwidth using the novel amplifier design techniques. Many examples are presented for the potential gain characteristics of the chosen low‐noise or ordinary types of transistor. © 2002 Wiley Periodicals, Inc. Int J RF and Microwave CAE 12, 483–495, 2002. Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mmce.10049     

Numerical calculation of the reflectance of sub-wavelength structures on silicon nitride for solar cell application

In this study, we calculate the spectral reflectivity of pyramid-shaped silicon nitride (Si₃N₄) sub-wavelength structures (SWS). A multilayer rigorous coupled-wave approach is advanced to investigate the reflection properties of Si₃N₄ SWS. We examine the simulation results for single layer antireflection (SLAR) and double layer antireflection (DLAR) coatings with SWS on Si₃N₄ surface, taking into account effective reflectivity over a range of wavelengths and solar efficiency. The results of our study show that a lowest effective reflectivity of 1.77% can be obtained for the examined Si₃N₄ SWS with the height of etched part of Si₃N₄ and the thickness of non-etched layer of 150 and 70 nm, respectively, which is less than the results of an optimized 80 nm Si₃N₄ SLAR (∼5.41%) and of an optimized DLAR with 80 nm Si₃N₄ and 100 nm magnesium fluoride (∼5.39%). 1% cell efficiency increase is observed for the optimized Si solar cell with Si₃N₄ SWS, compared with the cell with single layer Si₃N₄ antireflection coatings (ARCs); furthermore, compared with DLAR coated solar cell, the increase is about 0.71%. The improvement on the cell efficiency is mainly due to lower reflectance of Si₃N₄ SWS over a wavelength region from 400 to 600 nm that leads to lower short circuit current.     

Estimation of nitrogen,phosphorus, and potassium contents in the leaves of different plants using laboratory-based visible and near-infrared reflectance spectroscopy: comparison of partial least-square regression and support vector machine regression methods

Nitrogen, phosphorus, and potassium are some of the most important biochemical components of plant organic matter, and hence, estimation of their contents can help monitor the metabolism processes and health of plants. This study, conducted in the Yixing region of China, aimed to compare partial least squares regression (PLSR) and support vector machine regression (SVMR) methods for estimating the nitrogen (C _N), phosphorus (C _P), and potassium (C _K) contents present in leaves of diverse plants using laboratory-based visible and near-infrared (Vis-NIR) reflectance spectroscopy. A total of 95 leaf samples taken from rice, corn, sesame, soybean, tea, grass, shrub, and arbour plants were collected, and their C _N, C _P, C _K, and Vis-NIR reflectance data were measured in a laboratory. The PLSR and SVMR methods were calibrated to estimate the C _N, C _P, and C _K contents of the obtained samples from spectral reflectance. Cross-validation with an independent data set was employed to assess the performance of the calibrated models. The calibration results indicated that the PLSR method accounted for 59.1%, 50.9%, and 50.6% of the variation of C _N, C _P, and C _K, whereas the SVMR method accounted for more than 90% of the variation of C _N, C _P, and C _K. According to cross-validation, the SVMR method achieved better estimation accuracies, which had determination coefficients of 0.706, 0.722, and 0.704 for C _N, C _P, and C _K, respectively, than the PLSR method, which had determination coefficients of 0.663, 0.643, and 0.541. It was concluded that the SVMR method combined with laboratory-based Vis-NIR reflectance data has the potential to estimate the contents of biochemical components.     

A standard deviation based firefly algorithm for multi-objective optimization of WEDM process during machining of Indian RAFM steel

Non-conventional machining processes always suffer due to their low productivity and high cost. However, a suitable machining process should improve its productivity without compromising product quality. This implies the necessity to use efficient multi-objective optimization algorithm in non-conventional machining processes. In this present paper, an effective standard deviation based multi-objective fire-fly algorithm is proposed to predict various process parameters for maximum productivity (without affecting product quality) during WEDM of Indian RAFM steel. The process parameters of WEDM considered for this study are: pulse current (I), pulse-on time (T _on), pulse-off time (T _off) and wire tension (WT).While, cutting speed (CS) and surface roughness (SR) were considered as machining performance parameters. Mathematical models relating the process and response parameters had been developed by linear regression analysis and standard deviation method was used to convert this multi objective into single objective by unifying the responses. The model was then implemented in firefly algorithm in order to optimize the process parameters. The computational results depict that the proposed method is well capable of giving optimal results in WEDM process and is fairly superior to the two most popular evolutionary algorithms (particle swarm optimization algorithm and differential evolution algorithm) available in the literature.

     

Switching performances of static induction thyristor with buried-gate structure

The switching characteristics of SITh are not only determined by the conductance modulation in channel between the gate regions,but also affected by the external gate driving circuit.The physical mechanism and behavior of switching process are studied deeply based on the fabrication practice of SITh.The dependence of switching performances of SITh on material,geometric structure and technological parameters are analytically discussed by using two-dimensional dynamical model firstly proposed in this paper.A series of optimum matching technological approaches have been developed for improving the switching characteristics of SITh.A versatile testing circuit is designed to get more accurate switching parameters and more stable switching-off process with lower power consumptions.The switching times ton and toff are reduced from 0.2μs and 1.2μs to 0.08μs and 1.0μs,respectively,and the dynamic dv/dt value of more than 1000 V/μs at switching-off is obtained.     

General circular permutation layout

In thegeneral circular permutation layout problem there are two concentric circles,C _in andC _out. There are a set ofn inner terminals onC _in and a set ofn outer terminals onC _out: terminalsi onC _in and _i onC _out are to be connected by means of a wire, where 1 i n. All wires must be realized in the interior ofC _out. Each wire can intersectC _in at most once and at mostK wires, for a fixedK, can pass between two adjacent inner terminals. A linear-time algorithm for obtaining a planar homotopy (single-layer realization) of an arbitrary instance of the general circular permutation layout problem, forK 0, is proposed. Previously,K = 1 has been studied. In this paper the algorithm is also extended to a more general problem, in which the number of wires allowed to pass between each pair of adjacent terminals onC _in may be different from pair to pair.The work of R. D. Lou and M. Sarrafzadeh was supported in part by the National Science Foundation under Grants MIP-8709074 and MIP-8921540. C. S. Rim, K. Nakajima, and S. Masuda's work was supported in part by the National Science Foundation under Grants MIP-8451510 and CDR-8803012 (Engineering Research Centers Program), and a grant from AT&T.