嵌入式控制系统在分布式测控系统中的应用

分布式测控系统以其测控范围广、构建成本低等优势而得到广泛的应用,本文针对嵌入式控制系统在分布式测控系统中的应用展开了分析讨论,给出了完整的分布式测控系统的系统架构与系统层次功能的设计方案,并在此基础上重点对嵌入式控制系统,从硬件设计和软件设计两个角度完成了嵌入式分布测控系统的构建方案,对于进一步提高分布式测控系统,以及嵌入式控制系统在分布式网络中的应用均具有一定的借鉴和指导意义。     

基于组件的嵌入式软件开发中的几个关键问题

针对嵌入式系统的实际特性,着重从系统的角度提出构造一个嵌入式应用程序的开发架构,也可以称为开发框架.该开发架构是以基于组件的方法来开发嵌入式应用程序的,其主要研究系统结构规约、系统行为规约、组件配置和执行、程序产生和系统配置等几个关键问题.研究的结果将指导一个分布嵌入式应用程序开发框架的构造.     

基于TTA的嵌入式ASIP设计

在嵌入式微处理器设计中,采用ASIP（application specific instruction processor）处理器设计方法,可以在满足功能和性能要求的同时,缩短嵌入式微处理器产品的研制时间．当前ASIP处理器设计方法还面临着许多问题,如体系结构优化、软件代码的可重定向编译等,这些都阻碍了ASIP处理器设计方法的广泛应用．因此,提出了一种基于传输触发体系结构（transport triggered architecture,TTA）的嵌入式ASIP设计方法,对其设计关键技术进行了详细的讨论,并通过两个目标应用的ASIP微处理器设计实例说明了该方法可以有效解决上述问题,快速开发出满足目标应用程序要求的嵌入式处理器。     

计算机系统在自动化仪器仪表中的应用

随着各领域技术的迅速发展和不断进步,计算机技术逐渐渗透到自动化控制技术中,其中,嵌入式计算机系统已经在仪器仪表领域获得了越来越多的应用。如今,自动化仪器仪表已具备＂工业IT＂的特征。本文首先介绍了我国仪器仪表控制系统的发展历程,阐述了嵌入式计算机系统的定义、特征、基本构架以及嵌入式计算机系统中的软件技术,对嵌入式计算机系统在仪器仪表中的应用进行了研究与分析,并展望了高级嵌入式系统对未来新型仪器仪表技术的支持及其前景。     

基于CISC/RISC混合架构的嵌入式MCU设计

CISC与RISC是目前微控制器（MCU）设计的两种主要指令体系。从MCU的架构原理入手分析基于这两种指令体系的MCU的各自功能特点,说明对于不同应用系统所需的嵌入式MCU设计所要考虑的基本问题及关键模块的设计方法。最后,以一款自主设计的八位MCU与CISC型微控制器MCS51、RISC型微控制器PIC16C54的性能作比较,说明基于CISC/RISC混合架构的MCU的一些性能优势。     

Exploring embedded-systems architectures with Artemis

Because embedded systems mostly target mass production and often run on batteries, they should be cheap to realize and power efficient. In addition, they require a high degree of programmability to provide real-time performance for multiple applications and standards. However, performance requirements as well as cost and power-consumption constraints demand that substantial parts of these systems be implemented in dedicated hardware blocks. As a result, their heterogeneous system architecture consists of components ranging from fully dedicated hardware components for time-critical application tasks. Increasingly, these designs yield heterogeneous embedded multiprocessor systems that reside together on a single chip. The heterogeneity of these highly programmable systems and the varying demands of their target applications greatly complicate system design. The increasing complexity of embedded-system architectures makes predicting performance behavior more difficult. Therefore, having the appropriate tools to explore different choices at an early design stage is increasingly important. The Artemis modeling and simulation environment aims to efficiently explore the design space of heterogeneous embedded-systems architectures at multiple abstraction levels and for a wide range of applications targeting these architectures. The authors describe their of this methodology in two studies that showed promising results, providing useful feedback on a wide range of design decisions involving the architectures for the two applications     

AQuoSA—adaptive quality of service architecture

This paper presents an architecture for quality of service (QoS) control of time‐sensitive applications in multi‐programmed embedded systems. In such systems, tasks must receive appropriate timeliness guarantees from the operating system independently from one another; otherwise, the QoS experienced by the users may decrease. Moreover, fluctuations in time of the workloads make a static partitioning of the central processing unit (CPU) that is neither appropriate nor convenient, whereas an adaptive allocation based on an on‐line monitoring of the application behaviour leads to an optimum design. By combining a resource reservation scheduler and a feedback‐based mechanism, we allow applications to meet their QoS requirements with the minimum possible impact on CPU occupation. We implemented the framework in AQuoSA (Adaptive Quality of Service Architecture (AQuoSA). http://aquosa.sourceforge.net ), a software architecture that runs on top of the Linux kernel. We provide extensive experimental validation of our results and offer an evaluation of the introduced overhead, which is perfectly sustainable in the class of addressed applications. Copyright © 2008 John Wiley & Sons, Ltd.     

Designing embedded systems using patterns: A case study

If software for embedded processors is based on a time-triggered architecture, using co-operative task scheduling, the resulting system can have very predictable behaviour. Such a system characteristic is highly desirable in many applications, including (but not restricted to) those with safety-related or safety-critical functions. In practice, a time-triggered, co-operatively scheduled (TTCS) architecture is less widely employed than might be expected, not least because care must be taken during the design and implementation of such systems if the theoretically predicted behaviour is to be obtained. In this paper, we argue that the use of appropriate ‘design patterns’ can greatly simplify the process of creating TTCS systems. We briefly explain the origins of design patterns. We then illustrate how an appropriate set of patterns can be used to facilitate the development of a non-trivial embedded system.     

The QC-2 parallel Queue processor architecture

Queue based instruction set architecture processor offers an attractive option in the design of embedded systems. In our previous work, we proposed a novel queue processor architecture as a starting point for hardware/software design space exploration for embedded applications. In this paper, we present a high performance 32-bit Synthesizable QueueCore (QC-2)—an improved and optimized version of the produced order parallel Queue processor (PQP), with single precision floating-point support. The QC-2 core also implements a novel technique used to extend immediate values and memory instruction offsets that were otherwise not representable because of bit-width constraints in the PQP processor.     

配置流驱动计算体系结构指导下的ASIP设计

为了兼顾嵌入式处理器设计中的灵活性与高效性,提出配置流驱动计算体系结构.在体系结构设计中将软/硬件界面下移,使功能单元之间的互连网络对编译器可见,并由编译器来完成传输路由,从而支持复杂但更为高效的互连网络.在该体系结构指导下,提出一种支持段式可重构互连网络的专用指令集处理器(ASIP)设计方法.该方法应用到密码领域的3类ASIP设计中表明,与简单总线互连相比,在不影响性能的前提下,可平均节约53%的互连功耗和38.7%的总线数量,从而达到减少总线数量、降低互连功耗的目的.     

基于一个实时内核的嵌入式Internet技术的研究与实现

基于微内核体系结构的思想，从嵌入式系统开发Internet应用的角度，提出一个实时内核-Webitx的软件体系结构及设计方案。为支持嵌入式Internet环境下的复杂应用，WebitX被设计成一个基于优先级的抢占式多任务内核，解决了任务调度、任务间同步与通信、定时管理、网络协议处理等主要问题，为嵌入式Internet应用提供了完备的系统服务，确保了嵌入式Internet应用的实时性和可靠性。为实现嵌入式设备与Internet的互联，WebitX提供了一个嵌入式TCP／IP协议栈，该协议栈在嵌入式系统资源受限的条件下，采用模块化的方法实现了TCP／IP协议簇的一个功能子集，为传统设备提供了网络接口，从而实现了高效的嵌入式Internet通信。     

图形化嵌入式开发平台的通用性设计

针对目前嵌入式开发平台的缺陷,在深入分析多系列MCU共性的基础上,利用软件构件的思想,提出了一种通用的图形化嵌入武开发平台的设计架构,并将其运用于多款MCU的实际开发中,达到了降低开发难度、减少开发时间的目的.提出的设计架构可为同类应用借鉴.     

The TMS34010: an embedded microprocessor

The authors discuss the TMS34010, a high-performance 32-bit microprocessor with special instructions and hardware for handling the bit-field data and address manipulations often associated with computer graphics. They give a history of embedded microprocessors and examine the wide range of processors and applications covered by that term. They provide an overview of the internal architecture of the TMS34010 and discuss the choice of feature set in its design. Although it is aimed at graphics systems, the processor's large address reach, bit-field processing, and DRAM (dynamic random-access memory) interface make it suitable for many other embedded processing applications.<>     

一种面向数字信号处理的嵌入式处理器体系结构设计

针对数字信号处理在嵌入式领域中的广泛应用，并基于数字信号处理程序的特征，本文提出了一种专门面向嵌入式应用中数字信号处理的处理器体系结构。该体系结构的设计建立在传输触发体系结构的基础上，并加入了针对sin／cos求值的特殊功能单元对性能进行加速。测试结果表明，这种体系结构对数字信号处理核心程序的运行具有极高的性
性能，并且具有硬件结构简单、易于开发的特征。     

Enhancing image processing architecture using deep learning for embedded vision systems

In recent years, the success and capabilities of embedded vision have showed up in embedded applications. The embedding of vision into electronic devices such as embedded medical applications is being driven by the availability of high-performance processors, integrating with deep learning algorithms, as well as advances in image processing technology. But, including image processing in embedded vision systems need huge amount of computational capabilities even to process a single image to detect an object and it's extremely challenging to implement in embedded systems. Implementing deep learning algorithms and testing it on a task specific data set could provide enhanced results. In this paper, an approach for enhancing image processing architecture using deep learning for embedded vision systems is proposed and analyzed. Implementing deep learning algorithms and testing it on embedded vision yielded effective results.     

Design and implementation of embedded computer vision systems based on particle filters

Particle filtering methods are gradually attaining significant importance in a variety of embedded computer vision applications. For example, in smart camera systems, object tracking is a very important application and particle filter based tracking algorithms have shown promising results with robust tracking performance. However, most particle filters involve vast amount of computational complexity, thereby intensifying the challenges faced in their real-time, embedded implementation. Many of these applications share common characteristics, and the same system design can be reused by identifying and varying key system parameters and varying them appropriately. In this paper, we present a System-on-Chip (SoC) architecture involving both hardware and software components for a class of particle filters. The framework uses parameterization to enable fast and efficient reuse of the architecture with minimal re-design effort for a wide range of particle filtering applications as well as implementation platforms.     

Towards embedded model predictive control for System-on-a-Chip applications

We propose a framework for embedding model predictive control for Systems-on-a-Chip applications. In order to allow the implementation of such a computationally expensive controller on chip, we propose reducing the precision of the microprocessor to the minimum while maintaining near optimal control performance. Taking advantage of the low precision, a logarithmic number system based microprocessor architecture is used, that allows the design of a reduced size processor, providing further energy and computational cost savings. The design parameters for this high-performance embedded controller are chosen using a combination of finite element method simulations and bit-accurate hardware emulations in a number of parametric tests. We provide the methodology for choosing the design parameters for two particular control problems; the temperature regulation in a wafer cross-section geometry, and the control of temperature in a non-isothermal fluid flow problem in a microdevice. Finally, we provide the microprocessor architecture details and estimates for the performance of the resulting embedded model predictive controller.     

A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems

With Moore’s law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embedded systems exacerbates this design challenge and necessitates the architectural modeling of embedded systems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embedded systems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We verify our queueing theoretic modeling approach by running SPLASH-2 benchmarks on the SuperESCalar simulator (SESC). Results reveal that our queueing theoretic model qualitatively evaluates multi-core architectures accurately with an average difference of 5.6% as compared to the architectures’ evaluations from the SESC simulator. Our modeling approach can be used for performance per watt and performance per unit area characterizations of multi-core embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.     

μITRON for small-scale embedded systems

The μITRON standard real-time kernel specification for small-scale embedded control systems has been implemented in a large number of microcontrollers and applications. We describe the design principles of the specification and the current state of its implementations and applications. We also introduce the μITRON bus, a low-cost real-time LAN standard for connecting small-scale embedded systems     

Design and implementation of high-speed buffered crossbars with efficient load balancing for multi-core SoCs

A large increase of the number of devices integrated in a single chip in conjunction with the significant demands of modern applications for performance has led the designers to a system development methodology based on integrating multiple pre-verified intellectual property cores. Yet, design productivity requirements push designers to focus on key micro-architectural solutions to manage more efficiently the scaling of multi-core SoCs as well as to increase the degree of design automation, particularly as rapid prototyping using reconfigurable computing is becoming mainstream. In this paper we present a novel interconnect architecture based on optimized components to efficiently manage SoCs that follow either a multi-core based approach or are built to support SIMD-style applications that can exploit the processing power of a pool of hardware resources; first we analyze the design of a crossbar featuring shared-memory combined input-crosspoint buffering as a solution for efficient implementation of on-chip interconnection; second we describe the design of a load-balancer featuring configurable proportional allocation of on-chip resources and in-order delivery as a solution for efficient scheduling and execution of processing tasks. The main focus of the paper is to describe and evaluate the mechanisms designed to distribute and manage data transfers so as to implement an efficient interconnection of the integrated cores and control access to available (either on-chip or off-chip) resources for the implementation of a number of embedded systems and applications. Each of these challenges is handled by the proposed architecture in an efficient way in terms of performance, cost in silicon and flexibility.