一种改进的片内ESD保护电路仿真设计方法

对现有的片内ESD保护电路仿真设计方法进行了改进,使之适用于深亚微米工艺.文中设计了新的激励电路以简化仿真电路模型;增加了栅氧化层击穿这一失效判据;使用能量平衡方程描述深亚微米MOSFET的非本地输运,并对碰撞离化模型进行了修正;使用蒙特卡罗仿真得到新的电子能量驰豫时间随电子能量变化的经验模型.最后使用文中改进的仿真设计方法对一个ESD保护电路进行了设计和验证,测试结果符合设计要求.     

VCO Design With On-Chip Calibration System

This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from$-$120.5 dBc/Hz to$-$118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the$K_ VCO$peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method.     

一种带温度和工艺补偿的片上时钟振荡器

基于SMIC0.18gm 1P6M的标准CMOS工艺,设计并实现了一种带温度补偿和工艺偏差校准的60MHz片上CMOS时钟振荡器.经仿真和流片测试验证,该结构的时钟振荡器输出频率能很好的稳定在60-61MHz,温度从-25℃变化至75℃时,频率仅变化108.5kHz,在对时钟精度要求不高的应用下,完全可以取代片外的石英晶振,降低成本.     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems

We present a 32 times 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mum times 56 mum , while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mum CMOS process.     

一种简化的片上螺旋电感双π等效电路模型

提出了一种简化的片上螺旋电感双π等效电路模型。该模型可有效的反映螺旋电感中的趋肤效应、邻近效应、衬底耦合、馈通电容、导体间电容等分布效应的影响。推导了该模型中元件的估算公式。由该估算公式得出的元件参数，可作为与实际数据拟合的参考值，从而提高了拟合的效率与准确性。经拟合后的等效电路模型，在0．1～10GHz范围内，与电磁场仿真软件(ADS momentum)所得的仿真结果有很好的一致性。     

A Simplified Calibration of Two-Port Transmission Line Devices

During the evaluation measurements of several two-port junction devices over a wide band of frequencies the authors found that the method of shorts as described in three previous papers was too laborious to be practical. By reinterpreting and combining the ideas of earlier authors, a valuable simplification was obtained. Since this paper is based upon the previous articles, no fundamental proofs will be given except to show the necessary extensions involved.     

基于多光刻胶有效扩散长度的光学临近效应修正模型校准方法

提出了基于多光刻胶有效扩散长度的光学临近效应修正模型校准方法,其考虑了一维和二维图形之间光刻胶有效扩散长度的不同. 该方法的一个重要步骤在于建立起全新的校准流程,使得一维图形和二维图形具有相同的光学参数和不同的光刻胶有效扩散长度. 另外,在该模型校准流程中提出了一种基于可制造性设计理念的交互. 从校准结果的关键尺寸误差及仿真轮廓和扫描电子显微镜图像的对比来看,基于多光刻胶有效扩散长度的光学临近效应修正模型校准方法的输出模型更加精确和稳定.     

基于多光刻胶有效扩散长度的光学临近效应修正模型校准方法

提出了基于多光刻胶有效扩散长度的光学临近效应修正模型校准方法,其考虑了一维和二维图形之间光刻胶有效扩散长度的不同.该方法的一个重要步骤在于建立起全新的校准流程,使得一维图形和二维图形具有相同的光学参数和不同的光刻胶有效扩散长度.另外,在该模型校准流程中提出了一种基于可制造性设计理念的交互.从校准结果的关键尺寸误差及仿真轮廓和扫描电子显微镜图像的对比来看,基于多光刻胶有效扩散长度的光学临近效应修正模型校准方法的输出模型更加精确和稳定.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法.该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点,将它们混合插入到连线的合适位置,从而降低互连的延时和功耗.模拟结果表明,该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

Hybrid Branchline Couplers -- A Useful New Class of Directional Couplers

The hybrid branchline coupler consists of two transmission lines connected alternately by /spl lambda//4 shunt and series branches. The analysis of this structure leads to a class of directional couplers of which the parallel transmission-line and the de Ronde strip-slot types may be regarded as special cases. From the precise design data thus available, a number of 3-dB strip-slot couplers have been built in C band and X band with a performance close to the predicted one.     

一种用于片上静电防护的新型闩锁免疫可控硅

可控硅(SCR)被广泛应用于片上静电放电(ESD)防护。由于SCR的低维持电压特性,闩锁问题一直是其应用于高压工艺ESD防护的主要问题。改进设计了一种新型SCR器件,即MOS High-holding Voltage SCR (MHVSCR)。通过对SCR寄生三极管正反馈进行抑制,并提高维持电压,实现了闩锁免疫。详细分析了MHVSCR提高SCR维持电压的可行性、工作原理以及实现步骤。基于Sentaurus TCAD的仿真结果表明:设计的器件将传统器件的SCR维持电压从2.8 V提高至15.88 V,有效实现了SCR在12 V工艺下的闩锁免疫能力。     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

Phase-Encoding for On-Chip Signalling

A novel self-timed communication protocol is based on the phase-modulation of a reference signal. The reference signal is sent on a number of transmission lines and the data can be recovered observing the sequence of events on the these lines. Employing several lines increases the number of states hence reducing the number of symbols required for a transmission. A new encoding algorithm is described which generates symbol-dependent matrices which are used to control the phase of transmission lines. The protocol concept, the algorithm and analysis of the system, together with simulation results, are presented.     

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

A dynamic-reconfigurable memory chip is fabricated, by which on-chip memories of an SoC chip can be moved to the memory chip to increase the efficiency of memory usage, and stacked on a logic chip by using three dimensional packaging technology. In the memory chip, many RAM-macros are arrayed and they are connected through two dimensional mesh network interconnects. By using memory-specified network interconnects, area overhead of network interconnects for the memory chip is reduced by 63% and the latency overhead by 43%. Signal lines between the two chips are directly connected by 10-?m-pitch inter-chip electrodes, resulting in fast and low-energy inter-chip transmission.     

一种片内信号间的相位检测与同步电路

提出了一种片内信号间的相位检测与同步电路。该电路通过检测信号间的相位信息,连续调整其中一个信号的延迟,从而保持信号与信号之间始终处于设定的相位同步关系。介绍了相位检测与同步电路的原理及结构,给出了每一个模块的具体电路结构并加以分析。基于SMIC 65 nm CMOS工艺,采用Cadence Spectre进行仿真,结果表明,电路可产生16个固定的相位关系,工作在1~4 GHz的宽频范围,在4 GHz工作频率时功耗为52 mW,而芯片尺寸为450 μm×450 μm。     

A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors

A novel compact model for on-chip vertically coiled spiral inductors is presented. The vertical metal coils are modeled by a ladder network consisting of ideal inductors and resistors. The skin and proximity effects are taken into consideration. The capacitive parasitics between relevant metal layers are modeled. A method to analytically extract the model parameters is proposed. The model prediction shows excellent agreement between the data from both simulation and measurement over the frequency range of 0.1–66.1 GHz, for a vertically coiled spiral inductor manufactured in TSMC 90 nm RF CMOS technology.     

实用棱镜耦合器的设计

设计了一种用于 YIG 薄膜光波导输出耦合的装置,该耦合器具有结构简单、制作与使用方便及实用性强等特点。     

一种基于BFT型拓扑结构片上网络低费用测试方法

随着集成电路制作工艺的进步,多核与众核系统是片上系统的发展趋势.传统的二维网格(2D-mesh)型拓扑结构通信效率低、功耗高和时延长等缺点变得越来越明显.本文首先分析对比了几种常用拓扑结构在多核与众核情况下的性能,进而采用布线复杂度较低、性能较好的蝴蝶型胖树(BFT)拓扑结构来解决片上系统的设计和测试问题.随后,本文针...     

Inductance Modeling for On-Chip Interconnects

As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.