Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

FinFET technology has become the most promising alternative to continue CMOS scaling due to its improved short channel effects. Design flexibility reduces on FinFET based circuits such as SRAM cells due to the effective channel width is determined by an integer number of fins. In this work, the impact of fin height size of FinFET transistors on the simultaneous behavior of soft error sensitivity and SRAM cell static noise margin is investigated. 3-D TCAD Sentarus environment is used to quantify the amount of collected and critical charges of an SRAM cell due to a heavy ion strike while Mix-Mode Hspice-TCAD simulation is used for stability analysis. Even more, the influence of process variations on sensitivity to soft errors and cell stability is considered. A 10 nm-SOI Tri-Gate FinFET technology is used. Results show that increasing the fin height of FinFET transistors considerably increases SRAM cell sensitivity to soft errors but improves its stability. This suggests that the optimum fin height value of FinFET transistors of an SRAM cell depends on the best tradeoff between soft error robustness and stability.     

Strained p-Channel FinFETs With Extended Π -Shaped Silicon–Germanium Source and Drain Stressors

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.     

Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.     

Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application

In this paper, Ta/Mo interdiffusion dual metal-gate technology, which has an advantage in realizing dual gate work functions without etching of metals from the gate dielectrics, has been introduced for a FinFET. Gate-first fabrication of the FinFET was successfully implemented by optimizing the deposition and patterning of the Mo and Ta/Mo metal gates on the ultrathin fin channels. The Ta/Mo-gated n-MOS and Mo-gated p-MOS FinFET exhibit symmetrical values of Vth (0.31/$-$0.36 V), which are desirable for FinFET CMOS circuit operation with enhanced current drivability, because the threshold voltage (Vth) is reduced due to Ta diffusion in the Ta/Mo gate. It was experimentally found that the Ta/Mo interdiffusion process causes no degradation in integrity of the gate dielectric or the carrier mobility. It was also confirmed that the Ta/Mo interdiffusion process is appropriate for a scaled gate length down to 100 nm.      

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

纳米FinFET的单粒子瞬态与Fin结构的相关性研究

工艺差异引起的Fin结构变化会造成纳米FinFET器件呈现不同的电学特性,使器件的单粒子瞬态效应(SET)复杂化。基于电学特性校准的14 nm SOI标准型FinFET器件,构建了弹头型、三角型、阶梯型、半圆型及底部椭圆型等5种结构,分析了SET的表征量与Fin结构参数间的相关性,并利用灰色理论,研究了它们之间的内在关联性。结果表明,器件的收集电荷量、沉积电荷量与Fin的截面积显著相关;SET电流峰值、电子-空穴对产生率峰值及双极放大系数同时依赖于Fin的截面积和等效沟道宽度,且对等效沟道宽度的依赖性更强。     

The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA

The effect of process variations of a FinFET-based low noise amplifier (LNA) are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate (IDDG) FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance (the desired value is 50 Ω purely real) of the LNA is compensated by the second gate bias of the IDDG FinFET.     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.     

Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables

The Fin field effect transistor (FinFET) is a multiple gate structure, which is recently emerging as a leading structure to continue the scaling of CMOS technology into the nanometer regime. This promising multiple gate structure has not only the advantage of reducing short channel effects but also of being compatible with the conventional planar CMOS technology. To our knowledge, this is the first letter addressing the nonlinear FinFET model validated by large signal network analyzer measurements. Here, we present a nonlinear FinFET model which is based on lookup tables. The accuracy of the developed model is completely and successfully verified through the comparison with nonlinear FinFET measurements     

Line-edge roughness induced single event transient variation in SOI FinFETs

The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (V_gs=0, V_ds=V_dd) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.     

Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs

A novel modified Schottky barrier p-channel FinFET (MSB FinFET) has been successfully demonstrated previously. In this paper, the detailed process conditions, especially the formation of MSB junctions, has been presented. Device characteristics as well as the geometry effect are also discussed extensively. In the MSB FinFETs fabricated by the two-step silicidation and implant-to-silicide techniques (ITS), an ultrashort and defect-free source/drain extension (SDE) could be formed at a temperature as low as 600/spl deg/C, resulting in excellent electrical characteristics. The ultrashort SDE could effectively thin out the SB width between source/channel during on-state or broaden and elevate it between drain/channel during off-state. A leakage mechanism of MSB FinFETs similar to the conventional ones was identified by the activation energy analysis. Strong fin width dependence of the electrical characteristics was also found in the proposed devices. When the fin width becomes larger than the silicide grain size, the multigrain structure results in a rough front edge of the MSB junction, which in turn degrades the short-channel device performance. This result indicates that the MSB device is suitable for use as FinFET. The low thermal budget of the MSB FinFET relaxes the thermal stability issue for metal gate/high-/spl kappa/ dielectric integration. It is considered that the proposed MSB FinFET is a very promising nanodevice.     

Resistive Bridging Defect Detection in Bulk,FDSOI and FinFET Technologies

Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to address this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technologies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect.     

FinFET and MOSFET preliminary comparison of gate oxide reliability

In this work, the influence of gate oxide reliability on N channel FinFET and MOSFET characteristics has been preliminary compared. For similar oxide damage, the results show that the oxide wear out has larger effects on the functionality of the FinFET than on the MOSFET.     

14 nm FinFET栅围寄生电容的建模与拟合

提出了一种基于保角映射方法的14 nm鳍式场效应晶体管(FinFET)器件栅围寄生电容建模的方法。对FinFET器件按三维几何结构划分寄生电容的种类,再借助坐标变换推导出等效电容计算模型,准确表征了不同鳍宽、鳍高、栅高和层间介质材料等因素对寄生电容的依赖关系。为了验证该寄生电容模型的准确性,对不同结构参数的寄生电容进行三维TCAD仿真。结果表明,模型计算结果与仿真结果的拟合度好,准确地反映了器件结构与寄生电容之间的依赖关系。     

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher kappa value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high- gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE.     

High-performance p-type independent-gate FinFETs

We present, to our knowledge, the first successful integration of two independent gates on a p-type FinFET. These results also represent a significant performance improvement over previously reported Independent-Gate FinFET results. The devices have gate lengths ranging from 0.5 to 5 /spl mu/m, and designed fin thicknesses ranging from 25 to 75 nm. Electrical results show near-ideal subthreshold slopes in double-gate mode (both gates modulated simultaneously). Independent-Gate operation is also examined by modulating saturated drain current with both front and back-gate voltages independently. The results are compiled to analyze performance trends versus fin thickness and gate length.