基于扩展汉明码的BISR设计优化

BISR本质是自动实现电路内部纠错.为监督SARM中的176bit宽并行数据,提出一种基于扩展汉明码设计BISR电路的优化技术.将并行数据劈裂为两个模块,分别利用基于扩展汉明码的独立ECC,组建BISR架构.根据异或逻辑的可交换性,重排子运算项,建立XOR-Tree可合并项的特征图,观察与提取可以共用的子运算项,借助这种＂兼容＂策略优化XOR-Tree,在TSMC 90nm工艺中满足了降低时延和面积的工程要求.仿真结果显示,时延与面积分别降低了约28%和约35%,功耗降低约36%.最终时延为1.5ns,面积为6 200μm^2,功耗是0.54mW,表明了本优化方法的有效性.     

Low cost design of microprocessor EDAC circuit

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.     

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctuation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit techniques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V, while keeping 960MHz at 1.5 V; and 3) a reduction by 3.6/spl times/10/sup 5/ in soft-error rate compared with that of conventional ECC.     

Design and characterization of an error-correcting code for theSONET STS-1 tributary

The authors have designed and characterized a single-error-correcting (SEC), double-error-detecting (DED) code applicable to the STS-1 SONET format. They show that if two of the presently unallocated bytes in the path overhead field of STS-1 are assigned for error-correction coding (ECC), a {6208, 6195} shortened extended Hamming code can be implemented using as few as 660 gates plus a 1-kbyte RAM IC, achieving (O8.6×10^-3 P ₂²) BER reduction with 139 μs of signal delay. The authors explain how the existing BIP-8 error-monitoring byte of the STS-1 format could be integrated with the proposed ECC so that a net allocation of only one new STS-1 overhead byte is required for both error monitoring and error correction. The implementation method is such that all path, line, and section overhead functions in SONET can be performed at intermediate sites without requiring ECC decoding. The authors consider application alternatives and describe the forward-error-correction (FEC) circuit design and trial results. System issues are covered, including network delay, effects of error extension on BER, addition of double-error detection, performance monitoring, and options for intelligent network control and management of FEC functions. Codes related to their path-level design that are applicable to a number of other strategies for applying FEC in SONET are presented     

Public-key based access control in sensornet

Symmetric cryptography has been mostly used in security schemes in sensor networks due to the concern that public key cryptography (PKC) is too expensive for sensor devices. While these schemes are efficient in processing time, they generally require complicated key management, which may introduce high memory and communication overhead. On the contrary, PKC-based schemes have simple and clean key management, but cost more computational time. The recent progress in PKC implementation, specially elliptic curve cryptography (ECC), on sensors motivates us to design a PKC-based security scheme and compare its performance with the symmetric-key counterparts. This paper proposes a practical PKC-based access control for sensor networks, which consists of pairwise key establishment, local access control, and remote access control. We have implemented both cryptographic primitives on commercial off-the-shelf sensor devices. Building the user access control as a case study, we show that PKC-based protocol is more advantageous than those built on symmetric cryptography in terms of the memory usage, message complexity, and security resilience. Meanwhile, our work also provides insights in integrating and designing PKC-based security protocols for sensor networks.     

Efficient Implementation of Elliptic Curve Cryptography (ECC) for Personal Digital Assistants (PDAs)

Wireless devices are characterized by low computational power and memory. In addition to this wireless environment are inherently less secure than their wired counterparts, as anyone can intercept the communication. Hence they require more security. One way to provide more security without adding to the computational load is to use elliptic curve cryptography (ECC) in place of the more traditional cryptosystems such as RSA. As ECC provides the same level of security for far less key sizes, as compared to the traditional cryptosystems, it is ideal for wireless security. In this thesis we will investigate the different ways of implementing ECC on wireless devices such as personal digital assistants (PDAs). We will present our findings and compare the different implementations. In our implementation ECC over the field F ⁿ ₂ using optimal normal basis representation gives the best results.     

一种ECC校验算法的设计与实现

电可擦除可编程存储器(EEPROM)由于工艺结构的局限性而导致数据在存储过程中存在小概率的位反转问题。为解决该现象,设计了基于汉明码的纠错码(ECC)校验系统。结合EEPROM的结构特点和数据存储模式,该系统包含ECC校验码计算模块和数据检错纠错模块,每32 bit数据生成6 bit ECC校验码,具有1 bit/32 bit的纠错力。采用硬件描述语言Verilog HDL设计并实现了该ECC验证系统,并将其应用于基于串行外设接口(SPI)的EEPROM。仿真结果表明ECC验证系统可以保证数据的正确率,提高存储系统的可靠性。     

Performance Evaluation of Bluetooth Systems With LDI, Modified LDI, and NSD Receivers

Bluetooth is a popular short-range low-power radio standard for wireless personal area networks. Bluetooth transmitters employ Gaussian frequency shift keying (GFSK) and simple block codes for error correction. Recently, two new receiver designs for Bluetooth devices, which are the so-called modified limiter-discriminator detector with integrate-and-dump filtering (LDI) and noncoherent sequence detection (NSD), have been proposed in the literature. While the modified LDI receiver is a concatenation of a conventional LDI detector with an improved error-correction decoder, the NSD receiver fully takes into account the memory introduced by the GFSK. Both receivers have been shown to improve the Bluetooth system performance in terms of physical-layer metrics such as bit-error rate and packet-error rate. In this paper, we present a comprehensive performance evaluation considering practically more relevant metrics such as throughput, delay, and delay jitter at the medium-access control layer. To this end, we develop an evaluation framework, which includes the spatial distribution of Bluetooth devices, path loss, fading, realistic data traffic models, scheduling, automatic repeat request, and baseband packet selection. Our numerical and simulation results verify that the newly introduced Bluetooth receivers, especially NSD, offer a significant performance enhancement for Bluetooth systems in terms of practically relevant measures.     

Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.     

IPv6 Multicast Forwarding in RPL-Based Wireless Sensor Networks

In wireless sensor deployments, network layer multicast can be used to improve the bandwidth and energy efficiency for a variety of applications, such as service discovery or network management. However, despite efforts to adopt IPv6 in networks of constrained devices, multicast has been somewhat overlooked. The Multicast Forwarding Using Trickle (Trickle Multicast) internet draft is one of the most noteworthy efforts. The specification of the IPv6 routing protocol for low power and lossy networks (RPL) also attempts to address the area but leaves many questions unanswered. In this paper we highlight our concerns about both these approaches. Subsequently, we present our alternative mechanism, called stateless multicast RPL forwarding algorithm (SMRF), which addresses the aforementioned drawbacks. Having extended the TCP/IP engine of the Contiki embedded operating system to support both trickle multicast (TM) and SMRF, we present an in-depth comparison, backed by simulated evaluation as well as by experiments conducted on a multi-hop hardware testbed. Results demonstrate that SMRF achieves significant delay and energy efficiency improvements at the cost of a small increase in packet loss. The outcome of our hardware experiments show that simulation results were realistic. Lastly, we evaluate both algorithms in terms of code size and memory requirements, highlighting SMRF’s low implementation complexity. Both implementations have been made available to the community for adoption.     

ELIMINATING SPEED PENALTIES IN ECC PROTECTED MEMORY DESIGNS USING “BIT BYPASSING” TECHNIQUES

In deep sub-micron ICs,growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems,such as soft errors induced by radiation.Error Correction Code （ECC） along with scrubbing is an efficient method for protecting memories against these errors.However,the latency of coding circuits brings speed penalties in high performance applications.This paper proposed a ＂bit bypassing＂ ECC protected memory by buffering the encoded data and adding an identifying address for the input data.The proposed memory design has been fabricated on a 130 nm CMOS process.According to the measurement,the proposed scheme only gives the minimum delay overhead of 22.6％,compared with other corresponding memories.Furthermore,heavy ion testing demonstrated the single event effects performance of the proposed memory achieves error rate reductions by 42.9 to 63.3 times.     

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method.     

数字光纤直放站中CPRI协议的FPGA实现

为了实现对特定地区的低成本覆盖,将无线基站的控制部分和射频部分分离.介绍了公共通用无线接口(CPRI)协议的规范,给出了基于LATTICE半导体公司的LFE2M35E的FPGA实现方案.采用硬件描述语言Verilog HDL设计各个功能模块.软件平台是LATTICE半导体公司提供的IspLEVER Project Na...     

A compact on-chip ECC for low cost flash memories

A compact on-chip error correcting circuit (ECC) for low cost flash memories has been developed. The total increase in chip area is 2%, including all cells, sense amplifiers, logic, and wiring associated with the ECC. The proposed on-chip ECC, employing 10 check bits for 512 data bits, has been implemented on an experimental 64M-bit NAND flash memory. The cumulative sector error rate has been improved from 10^-4 to 10^-10. By transferring read data from the sense amplifiers to the ECC twice, 522-Byte temporary buffers, which are required for the conventional ECC and occupy a large part of the ECC area, have been eliminated. As a result, the area for the circuit has been drastically reduced by a factor of 25. The proposed on-chip ECC has been optimized in consideration of balance between the reliability improvement and the cell area overhead. The power increase has been suppressed to less than 1 mA     

A Symbiotic Evolutionary Design of Error‐Correcting Code with Minimal Power Consumption

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power‐efficient ECC which provides single‐error correction and double‐error detection (SEC‐DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

Lightweight Cryptography: A Solution to Secure IoT

In Internet of Things (IoT), the massive connectivity of devices and enormous data on the air have made information susceptible to different type of attacks. Cryptographic algorithms are used to provide confidentiality and maintain the integrity of the information. But small size, limited computational capability, limited memory, and power resources of the devices make it difficult to use the resource intensive traditional cryptographic algorithms for information security. In this scenario it becomes impertinent to develop lightweight security schemes for IoT. A thorough study on the lightweight cryptography as a solution to the security problem of resource-constrained devices in IoT has been presented in this work. This paper is a comprehensive attempt to provide an in-depth and state of the art survey of available lightweight cryptographic primitives till 2019. In this paper 21 lightweight block ciphers, 19 lightweight stream ciphers, 9 lightweight hash functions and 5 variants of elliptic curve cryptography (ECC) has been discussed i.e. in total 54 LWC primitives are compared in their respective classes. The comparison of the ciphers has been carried out in terms of chip area, energy and power, hardware and software efficiency, throughput, latency and figure of merit (FoM). Based on the findings it can be observed that AES and ECC are the most suitable for used lightweight cryptographic primitives. Several open research problems in the field of lightweight cryptography have also been identified.

     

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

Error Correction Schemes with Erasure Information for Fast Memories

Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions.     

A secure regenerating code‐based cloud storage with efficient integrity verification

Cloud storage is gaining popularity as it relieves the data owners from the burden of data storage and maintenance cost. However, outsourcing data to third‐party cloud servers raise several concerns such as data availability, confidentiality, and integrity. Recently, regenerating codes have gained popularity because of their low repair bandwidth while ensuring data availability. In this paper, we propose a secure regenerating code‐based cloud storage (SRCCS) scheme, which utilizes the verifiable computation property of homomorphic encryption scheme to check the integrity of outsourced data. In this work, an error‐correcting code (ECC)–based homomorphic encryption scheme (HES) is employed to simultaneously provide data privacy as well as error correction while supporting efficient integrity verification. In SRCCS, server regeneration process is initiated on detection of data corruption events in order to ensure data availability. The ECC‐based HES significantly reduces the probability of server regeneration and minimizes the repair cost. Extensive theoretical analysis and simulation results validate the security, efficiency, and practicability of the proposed scheme.