A wide-band tuning system for fully integrated satellite receivers

The building blocks for a low-power tuning system that reduces the phase noise of integrated VCO's are described. The multimodulus prescaler, the phase frequency detector, and the wide-band charge pump have been integrated in a standard bipolar technology with 9-GHz n-p-n transistors and 200-MHz p-n-p transistors. The maximum input frequency of the multimodulus prescaler is 3.2 GHz, the maximum reference frequency of the phase frequency detector is 380 MHz, and the 3-dB bandwidth of the charge pump is 41 MHz at a reference frequency of 300 MHz. The achieved performance enables the use of fully integrated VCO's with relatively high phase noise for reception of satellite digital signals     

A Ka-band micromachined low-phase-noise oscillator

A low-phase-noise 28.65 GHz oscillator has been demonstrated using a planar resonator. The resonator is micromachined close to the transistor and has an unloaded Q of 460. The oscillator uses a commercially available high electron mobility transistor (HEMT) for the active device, and results in an output power of 0.6 dBm with a 5.7% DC-RF efficiency. The measured phase noise is -92 dBc/Hz at a 100 kHz offset frequency and -122 dBc/Hz at 1 MHz offset frequency. This is compared with a low-Q planar design showing a 10 dB improvement in phase noise. The micromachined resonator is competitive with other hybrid nonplanar technologies, such as dielectric resonators     

A low-phase-noise voltage-controlled oscillator for 17-GHz applications

A silicon bipolar voltage-controlled oscillator (VCO) for 17-GHz applications is presented. The VCO is composed of a core oscillating at 9GHz followed by a frequency doubler. It adopts a transformer-based topology to obtain both wide tuning range and low noise performance. The VCO exhibits a tuning range of 4.1GHz from 16.4 to 20.5GHz and a phase noise as low as -109dBc/Hz at a 1-MHz frequency offset from a carrier of 18.5GHz.     

A low-phase-noise 900-MHz CMOS ring oscillator with quadrature output

A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW.     

应用于DVB电视调谐器的低相位噪声数控晶体振荡器设计

本文提出了一种全集成的25-MHz数字控制晶体振荡器。该数控晶体振荡器基于Colpitts结构实现。通过自动幅度控制电路实现相位噪声的优化。通过10位的温度计译码电容阵列实现自动频率控制。测试结果表明,该数控晶体振荡器在1kHz和10kHz频偏处的相位噪声分别为–139 dBc/Hz和–151 dBc/Hz。频率调谐范围约为35ppm,频率精度为0.04ppm。该数控晶体振荡器在SMIC 0.18μm CMOS工艺下实现,电源电压1.8V,消耗电流1mA。     

A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners

This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator(DCXO) with automatic amplitude control(AAC).The DCXO is based on Colpitts topology for one-pin solution.The AAC circuit is introduced to optimize the phase noise performance.The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array,ensuring a～35 ppm tuning range and～0.04 ppm frequency step.The measured phase noise results are-139 dBc/Hz at 1 kHz and-151 dBc/Hz at 10 k...     

A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator

A low voltage multiband all-pMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption.     

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator withprescaler

The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-μm CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW     

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noiseupconversion minimization

A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f³ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f³ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-μm BiCMOS process, using only MOS active devices     

Square-extensional mode single-crystal silicon micromechanical resonator for low-phase-noise oscillator applications

A micromechanical 13.1-MHz bulk acoustic mode silicon resonator having a high quality factor (Q=130 000) and high maximum drive level (P= 0.12 mW at the hysteresis limit) is demonstrated. The prototype resonator is fabricated of single-crystal silicon by reactive ion etching of a silicon-on-insulator wafer. A demonstration oscillator based on the new resonator shows single-sideband phase noise of -138 dBc/Hz at 1 kHz offset from the carrier.     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

A 1.57-GHz fully integrated very low-phase-noise quadrature VCO

A very low-phase-noise quadrature voltage-controlled oscillator is presented, featuring an inherently better figure of merit than existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit can be lowered. The circuit draws 15 mA from a 2-V supply. The phase noise is -133.5 dBc/Hz at 600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz     

Analysis of an oscillator consisting of digital integrated circuits

The authors present the theoretical and experimental investigations of an oscillator consisting of digital integrated circuits that act as nonlinear active elements. The circuit equation for this oscillator is derived from the inverse tangent approximation to the input-output characteristic of the digital IC. Using the perturbation method, the approximate solutions of this equation are obtained. The propriety of the inverse tangent approximation is ascertained by comparing the calculated and experimental value of the limit cycles.     

A 5-GHz fully integrated full PMOS low-phase-noise LC VCO

A 5-GHz fully integrated, full PMOS, low-phase-noise and low-power differential voltage-controlled oscillator (VCO) is presented. This circuit is implemented in a 0.35-/spl mu/m four-metal BiCMOS SiGe process. At 2.7-V power supply voltage and a total power dissipation of only 13.5 mW, the proposed VCO features a worst case phase noise of -97 dBc/Hz and -117 dBc/Hz at 100 kHz and 1 MHz frequency offset, respectively. The oscillator is tuned from 5.13 to 5.68 GHz with a tuning voltage varying from 0 to 2.7 V.     

A 67-GHz low-phase-noise oscillator and its application in a polar transmitter

In this paper, a low-phase-noise 67-GHz CMOS oscillator is presented. This inductorless voltage-controlled oscillator (VCO) employs a combination of standing-wave and travelling-wave oscillators to generate multi-phase outputs. A filtering technique is used to reduce the phase noise of the VCO. The oscillator achieves a tuning range of 5.2 GHz using a combination of coarse and fine tuning methods. The proposed multi-phase oscillator is designed and fabricated in a 0.13-μm CMOS process. Operating at 67 GHz, the VCO consumes 14 mW from a 1.2-V supply and achieves an output phase noise of −95.66 dBc/Hz (−107.89 dBc/Hz) at a 1 MHz (10 MHz) offset. The chip area is 0.9 mm². As an application example for the presented multi-phase oscillator, a polar transmitter structure is proposed. The transmitter is designed for systems that use a circular quadrature-amplitude modulation (QAM) constellation. A specific example of a 16-QAM transmitter is presented. The desired output phase is chosen by an 8-to-1 multiplexer, and a variable gain amplifier (VGA) is used to achieve the desired amplitude. Based on post-layout simulations, the 60-GHz 16-QAM transmitter consumes 43.2 mW from a 1.2-V supply.     

A 9.8-11.5-GHz quadrature ring oscillator for optical receivers

This paper describes a quadrature ring oscillator that is tunable from 9.8 to 11.5 GHz in a 30-GHz f_T BiCMOS technology. The ring oscillator can be used in advanced data clock recovery architectures in optical receivers. The circuit implementation of the oscillator uses transistors as active inductances. Isolation between the oscillator and cascaded circuits, such as buffers and flip-flops, is improved by utilizing the active inductances in a cascode configuration. Carrier to noise ratios better than 94 dBc/Hz at 2-MHz offset are measured with 75-mW dissipation and 2.7-V supply voltage. The evolution in two-stage ring oscillator topologies, leading to the realized design, is discussed in detail on the circuit level     

A sinusoidal voltage-controlled oscillator for integrated circuits

This article describes an inductorless near-harmonic voltage-controlled oscillator circuit that utilizes a compensated Wien-bridge topology with a voltage-controlled Miller integrator as the tuning element. Suitable for monolithic integrated realization, the VCO offers a two-to-one control range for frequencies up to 10 MHz, with less than a 1-dB amplitude variation and less than a ten percent total harmonic distortion over the entire control range.     

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator(DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18μm CMOS process with six metal layers.A third new way to change capacitance is proposed and implemented in this work.Results show that the phase noise at 1 MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also,the DCO can work at low supply voltage conditions with a 1.6 ...     

A GaAs monolithic 6 GHz low-noise amplifier for satellite receivers

A design approach and accurate modeling techniques developed to realize a GaAs monolithic, 6-GHz, two-stage, low-noise amplifier (LNA) with a measured 1.7 dB noise figure and associated 21 dB gain are discussed. This self-biased LNA design, with chip dimensions of 80 mil×135 mil, utilizes an ion-implantation FET model which predicts measured in-band amplifier gain to within 0.5 dB and peak frequency response to within 4%. The derived noise parameter estimation process, which uses a Gaussian elimination technique to predict the measured noise figure to within 0.2 dB, reduces a set of complex, binomial equations to simple relationships which are easily programmable. A deep-recessed gate realization of this LNA design demonstrates that LNA low-noise performance is achievable under FET saturated drain current conditions     

一种基于新型电容阵列的低功耗低相位噪声数字控制振荡器

摘要： 利用0.18CMOS六层金属工艺实现了一个全集成的低功耗低相位噪声的数字控制振荡器,该数字控制振荡器谐振回路由中央抽头对称螺旋电感和电容阵列构成。文中介绍并实现了一种新型的改变电容的方法。该方法在不需要改变接入谐振回路电容的数量而通过改变其互联拓扑关系来实现。测试结果表明,在1.8V电源电压下,核心模块消耗4.8mA的电流,相位噪声在1MHz频偏处为-122.5dBc/Hz。在1.6V的低电源电压,消耗约4mA的电流情况下,1MHz频偏处相位噪声仍可达到-121.5dBc/Hz. 同时,电源推挽度小于10MHz/V。