On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits

On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply voltages and multiple grounds are presented. Analytic models are also developed to estimate the loop inductance in four types of proposed power delivery schemes. Two proposed schemes, fully and pseudo-interdigitated power delivery, reduce power supply voltage drops as compared to conventional interdigitated power distribution systems with dual supplies and a single ground by, on average, 15.3% and 0.3%, respectively. The performance of the proposed on-chip power distribution grids is compared to a reference power distribution grid with a single supply and a single ground. The voltage drop in fully interdigitated and fully paired power distribution grids with multiple supplies and multiple grounds is reduced, on average, by 2.7% and 2.3%, respectively, as compared to the voltage drop of an interdigitated power distribution grid with a single supply and a single ground. The proposed power distribution grids are a better alternative to a single supply voltage and a single ground power distribution system. On-chip resonances in power distribution grids with decoupling capacitors are intuitively explained in this paper, and circuit design implications are provided. It is also noted that fully interdigitated and fully paired power distribution grids with multiple supply voltages and multiple grounds are recommended to decouple power supply voltages.     

Inductive properties of high-performance power distribution grids

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.     

高速集成电路电源网络的频率特性分析

提出了用一种简单模型计算随频率变化的电感。由于稠密的部分电感矩阵使得方程求解非常困难，采用二次求逆的方法对其进行处理。采用频变电感的计算方法，分析了三种类型电源网络的电感随频率变化的特性。由计算结果可知，网络的回路电感随信号频率的升高呈下降趋势，且成对分布的电源网络的回路电感最小。这为电源网络的设计和同步开关噪声的分析提供了一定的依据。     

飞机电源系统并排敷设导线阻抗特性分析

导线是飞机电源系统电能传输的主要载体。由于邻近效应,并排敷设相邻导线的电流有效值、频率等因素会影响导线阻抗值发生变化。为确定由于邻近效应引起的导线阻抗参数的变化,利用仿真软件Maxwell 2D/Simplorer建立并排敷设导线仿真模型,分析在邻近导线电流有效值、频率变化时,被测导线电阻、电感的变化规律,并对引起阻抗变化的原因进行了分析。结果表明：由于邻近效应和趋肤效应,被测导线的电阻值会随邻近导线电流频率和有效值的增大而增大;被测导线的电感值随邻近导线电流有效值的增大而增大,随邻近导线电流频率的增大而减小;在相同频率下,并排敷设时被测导线电阻、电感比单根敷设时大。     

Impedance characteristics of power distribution grids in nanoscale integrated circuits

The essential design characteristic of nanoscale integrated circuits is increased interconnect complexity. Conductors at different levels of the interconnect hierarchy have highly different physical and, consequently, electrical characteristics. These interconnect lines also exhibit inductive behavior due to enhanced switching speed of nanoscale devices, making interconnect design and analysis difficult. The design of robust and area efficient power distribution networks for high-speed integrated circuits has therefore become a challenging task. The impedance characteristics of multilayer power distribution grids and the relevant design implications are the subject of this paper. The power distribution network spans many layers of interconnect with disparate electrical properties. Unlike single-layer grids, the electrical characteristics of multilayer grids vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low-resistance upper layers to the low-inductance lower layers. The inductance of a multilayer grid therefore decreases with frequency, while the resistance increases with frequency. The lower layers of multilayer power grids provide a low-inductance current path, significantly reducing the grid impedance at high frequencies. Multilayer power distribution grids extend to the lower interconnect layers, exhibiting superior high-frequency impedance characteristics as compared to power distribution grids built exclusively within the upper, low-resistance metal layers. A significant share of metal resources to distribute the global power should therefore be allocated to the lower metal layers. An analytic model is also presented to determine the impedance characteristics of a multilayer grid from the inductive and resistive properties of the comprising individual grid layers.     

多导体传输线的邻近效应和分布参数研究

随着多导体传输线内各导体之间间距的减小, 导体之间的近邻效应对传输线的分布参数和传输特性的影响越来越大.为此, 我们针对三种典型的传输线结构, 分别建立了基于矢势有限元方法分析的多导体传输线的模型, 并分析了近邻效应对磁通密度和分布电感的影响.利用提出的方法计算了同轴传输线的单位长度分布电感, 并将它与采用解析方法得到的结果进行比较来证明该方法的正确性.计算双线传输线在不同间距时的单位长度电感, 与理论分析得到的结果相比较验证了导线间距越小, 近邻效应对单位长度电感的影响越大.最后, 计算考虑了近邻效应的耦合微带线的电感矩阵, 并将它与其他不考虑近邻效应的方法得到的结果相比较, 说明近邻效应对传输线电感矩阵的影响.     

多导体传输线瞬态响应研究

随着多导体传输线内各导体之间间距的减小, 导体之间的近邻效应对传输线的分布参数和传输特性的影响越来越大.为此, 我们针对三种典型的传输线结构, 分别建立了基于矢势有限元方法分析的多导体传输线的模型, 并分析了近邻效应对磁通密度和分布电感的影响.利用提出的方法计算了同轴传输线的单位长度分布电感, 并将它与采用解析方法得到的结果进行比较来证明该方法的正确性.计算双线传输线在不同间距时的单位长度电感, 与理论分析得到的结果相比较验证了导线间距越小, 近邻效应对单位长度电感的影响越大.最后, 计算考虑了近邻效应的耦合微带线的电感矩阵, 并将它与其他不考虑近邻效应的方法得到的结果相比较, 说明近邻效应对传输线电感矩阵的影响.     

High-frequency characterization of on-chip digital interconnects

On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic test structures that study the effect of mutual couplings to local interconnects, to random lines connected to on-chip drivers, and to typical power and ground grids. The use of S parameters to characterize the inductance allows a large number of lines to be extracted while requiring only a small overhead measurement of dummy open pads to remove measurement parasitics. It also enables direct extraction of the frequency-dependent R, L, G, C parameters. The results are summarized with curve-fitted formulas of inductance and resistance over a wide range of line spacings and line widths. The significance of the frequency dependence is illustrated with transient analysis of a typical repeater circuit in a 0.25-μm technology. A model that captures the frequency dependency of the extracted parameters accurately predicts the performance of a new inductance-sensitive ring oscillator     

Inductance Model of Interdigitated Power and Ground Distribution Networks

A closed-form expression is presented in this brief to accurately estimate the effective inductance of a single layer within an interdigitated power and ground (P/G) distribution network. Due to the large number of P/G lines in these networks, excessive time is required to calculate the inductance using 3-D simulation tools. The proposed expression is favorably compared with previous models and FastHenry, exhibiting accuracy and computational efficiency. The inductance of a single layer within an interdigitated P/G distribution network is bounded for any number of lines. The error of the proposed expression rapidly decreases with an increasing number of pairs within the network. The upper bound for the error of the proposed model is also determined.     

A Simple Model Parameter Extraction Methodology for an On‐Chip Spiral Inductor

In this letter, a simple model parameter extraction methodology for an on‐chip spiral inductor is proposed based on a wide‐band inductor model that incorporates parallel inductance and resistance to model skin and proximity effects, and capacitance to model the decrease in series resistance above the frequency near the peak quality factor. The wide‐band inductor model does not require any frequency dependent elements, and model parameters can be extracted directly from the measured data with some curve fitting. The validity of the proposed model and parameter extraction methodology are verified with various size inductors fabricated using 0.18 µm CMOS technology.     

A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications     

Frequency response characteristics of reference plane effectiveinductance and resistance [IC packaging]

A method which uses the partial element equivalent circuit (PEEC) method and electrical network theory to solve for the effective impedance matrix of reference planes is presented. The convergence and accuracy of the method are checked. The frequency responses of the effective inductance (L_eff(f)) and resistance (R_eff(f)) of reference plane are discussed. The effects of current redistribution and the skin effect on L_eff(f) and R _eff(f) are discussed. The effect of number of sinks and sources is examined     

Calculation of fault rates of overhead power distribution lines dueto lightning-induced voltages including the effect of groundconductivity

Fault rates in power distribution lines are estimated from probability distributions for induced voltages, obtained through a Monte Carlo simulation of lightning, striking in the proximity of a line over a finitely conductive ground. Waveshapes are presented for various locations relative to the point of interest along the line. The effects of line height, ground conductivity, and return stroke current risetime are analyzed. Results show that the expected number of faults increases for lower ground conductivities     

寄生电感对低压增强型GaN HEMT开关行为的影响

寄生电感是影响功率管开关特性的重要因素之一,开关频率越高,寄生电感对低压增强型氮化镓高电子迁移率晶体管(GaN HEMT)的开关行为影响越深,使其无法发挥高速开关的性能优势。通过建立数学模型,理论分析了考虑各部分寄生电感后增强型GaN HEMT的开关过程,并推导了各阶段的持续时间和影响因素,然后通过建立双脉冲测试平台,对各部分寄生电感对开关特性的具体影响进行了实验验证。实验结果表明,寄生电感会使开关过程中的电流、电压出现振荡,影响开关速度和可靠性,并且各部分寄生电感对增强型GaN HEMT的开关过程影响程度不同,在实际PCB布局受到物理限制时,需要根据设计目标优化布局,合理分配各部分寄生电感以获得最优的开关性能。     

Series resonant converter with auxiliary winding turns: analysis,design and implementation

Conventional series resonant converters have researched and applied for high-efficiency power units due to the benefit of its low switching losses. The main problems of series resonant converters are wide frequency variation and high circulating current. Thus, resonant converter is limited at narrow input voltage range and large input capacitor is normally adopted in commercial power units to provide the minimum hold-up time requirement when AC power is off. To overcome these problems, the resonant converter with auxiliary secondary windings are presented in this paper to achieve high voltage gain at low input voltage case such as hold-up time duration when utility power is off. Since the high voltage gain is used at low input voltage cased, the frequency variation of the proposed converter compared to the conventional resonant converter is reduced. Compared to conventional resonant converter, the hold-up time in the proposed converter is more than 40ms. The larger magnetising inductance of transformer is used to reduce the circulating current losses. Finally, a laboratory prototype is constructed and experiments are provided to verify the converter performance.     

一种双有源桥谐振变换器的研究与设计

以能量双向流动双有源桥(DAB)串联谐振变换器为研究对象,在考虑隔离变压器激磁电感和泄漏电感影响的基础上,建立双有源桥串联谐振变换器的准确等效模型,推导出其稳态工作特性。分析了DAB串联谐振变换器软开关条件和激磁电感最优值选择方法。设计了一种工作在谐振频率处的DAB串联谐振DC/DC变换器,当电压增益M=1时,所有开关在全负载范围内都工作,均能实现ZVS。还分析了负载变化时谐振电压和电流的变化规律。最后给出设计实例,并用SABER仿真软件搭建了实验电路,仿真结果验证了理论分析的有效性。     

寄生电感对碳化硅MOSFET开关特性的影响

相比于传统的Si IGBT功率器件而言,碳化硅MOSFET可达到更高的开关频率、更高的工作温度以及更低的功率损耗.然而,快速的暂态过程使开关性能对回路的寄生参数更加敏感.因此,为了评估寄生电感对碳化硅MOSFET开关性能的影响,基于回路电感的概念,将栅极回路寄生电感、功率回路寄生电感以及共源极寄生电感等效成3个集总电感,并且从关断过电压、开通过电流及开关损耗等3个方面,对这3个电感对SiC MOSFET开关性能的影响进行了系统的对比研究.研究表明:共源极寄生电感对开关的影响最大,功率回路寄生电感次之,而栅极回路寄生电感影响最小.最后,基于实验分析结果,为高速开关电路的布局提出了一些值得借鉴的意见.     

Improved transmission line model for high-frequency modelling of through silicon vias

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation.     

Exploiting the on-chip inductance in high-speed clock distributionnetworks

On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.