Structural characterization of thick, high-quality epitaxial Ge on Si substrates grown by low-energy plasma-enhanced chemical vapor deposition

In this paper, we report on the growth of epitaxial Ge on a Si substrate by means of low-energy plasma-enhanced chemical vapor deposition (LEPECVD). A Si_1?xGe_x graded buffer layer is used between the silicon substrate and the epitaxial Ge layer to reduce the threading dislocation density resulting from the lattice mismatch between Si and Ge. An advantage of the LEPECVD technique is the high growth rate achievable (on the order of 40 Å/sec), allowing thick SiGe graded buffer layers to be grown faster than by other epitaxial techniques and thereby increasing throughput in order to make such structures more manufacturable. We have achieved relaxed Ge on a silicon substrate with a threading dislocation density of 1 × 10⁵ cm^?2, which is 4?10x lower than previously reported results.     

Growth and electrical properties of the (Si/Ge)-on-insulator structures formed by ion implantation and subsequent hydrogen-assisted transfer

Systematic features of endotaxial growth of intermediate germanium layers at the bonding interface in the silicon-on-insulator structure consisting of buried SiO₂ layer implanted with Ge⁺ ions are studied in relation to the annealing temperature. On the basis of the results for high-resolution electron microscopy and thermodynamic analysis of the Si/Ge/SiO₂ system it is assumed that the endotaxial growth of the Ge layer occurs via formation of a melt due to enhanced segregation and accumulation of Ge at the Si/SiO₂ interface. Effect of germanium at the bonding interface on the Hall mobility of holes in silicon layers with nanometer-scale thickness is studied. It is found that the structures including the top silicon layer with the thickness 3–20 nm and incorporating germanium feature the hole mobility that exceeds by a factor of 2–3 the hole mobility in corresponding Ge-free silicon-on-insulator structures.     

Electrical characteristics of diodes fabricated in selective Si/Si1−x Ge x epitaxial layers

Diodes have been fabricated in layers of Si_1−x Ge _x and silicon deposited selectively on patterned wafers, and the electrical characteristics of the diodes have been examined. For 50 nm thick Si_1−x Ge _x layers containing about 22% Ge, the forward characteristics of larger diodes are nearly ideal. However, the reverse leakage current is higher when the edges of the diode intersect the oxide defining the selectively deposited layers than when the diode edges are separated from this oxide. The diode characteristics are more ideal when the diode edges are aligned along the [100] directions than when aligned along the [110] directions. Higher-temperature hydrogen pre-treatments before epitaxial deposition can degrade the diode characteristics.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

Growth and characterization of germanium and boron doped silicon epitaxial films

The epitaxial growth and characterization of in-situ germanium and boron (Ge/B) doped Si epitaxial films is described. As indicated by secondary ion mass spectroscopy and spreading resistance measurements, the total and electrically activated B concentrations are essentially identical and independent of Ge incorporation. The B and Ge concentrations are uniformly distributed in these Ge/B doped films. A slight enhancement of Hall mobility is obtained, possibly due to the stress relief induced by Ge counterdoping. Carrier conduction in these films is due to the activated B with an activation energy of 0.04 eV as revealed by conductivity versus temperature measurements. Ge atoms appear to be isoelectronic with Si atoms in these films. A slight degradation of minority carrier diffusion length is observed. Electrical characterization of PN diodes on these Ge/B doped films do not reveal any anomaly. SiO₂ on these Ge/B doped films has similar oxide fixed charge density, interface state density and dielectric breakdown strength compared to silicon dioxide on boron doped epitaxial films. Electron injection reveals a different transport mechanism of the SiO₂ grown on these Ge/B doped films.     

锗纳米线的性能与应用

重点分析讨论了锗纳米线在电学、光学、光电导等特性及其在场效应晶体管制造方面的研究应用现状与最新进展。综合分析表明,未经处理的锗纳米线表面存在一层氧化物及缺陷,与电极连接时欧姆接触性能较差,在制备锗纳米线器件以前必须对锗纳米线表面进行钝化以便沉积电极;对锗纳米线进行掺杂可以改善Ge纳米线的性能,制造出实用Ge纳米线器件。指出在一根纳米线上生长硅/锗半导体纳米线形成硅/锗半导体界面,直接用单根纳米线制造具有完整功能的电子器件是将来重要的研究方向。     

Silicon preamorphization and shallow junction formation for ULSI circuits

The effects of preamorphization of silicon by¹⁹F,²⁸Si and⁷⁴Ge implants preceding¹¹B implants have been investigated in this work and compared with BF₂ molecular implants. For shallow boron implanted layers less than 0.2 μm deep, the beam purity of BF₂ implants is crucial as well as proper preamorphization of the silicon to eliminate any inadvertent channeling. Preamorphization of silicon can be achieved with either⁷⁴Ge,²⁸Si or¹⁹F implants. Data from SIMS, TEM, RBS and diode leakage current measurements have all consistently shown that the best results are obtained with⁷⁴Ge preamorphization, followed by²⁸Si- and¹⁹F-preamorphization. RTA of preamorphized silicon at 1000° C for 10s in a dry argon ambient is preferred for shallow junctions. Furnace anneals at 950° C for 45 min of⁷⁴Ge preamorphized samples have resulted in practically perfect PN junctions.     

Anodic passivation of SiGe

We have investigated the oxide composition and the electronic behavior of the interface of anodically and thermally oxidized SiGe single crystals and epitaxial layers. X-ray photoelectron spectroscopies show the existence of SiO₂, GeO₂ and possibly mixed oxide compounds such as SiOGe only in the anodic oxide, whereas the thermally grown oxide layers on SiGe samples consist of pure SiO₂. In addition, the Ge enrichment at the interface and relaxation phenomena of the strained SiGe lattice of epitaxial layers, which occurs during thermal treatments, are completely reduced using the anodic treatment. Further, the defect concentration at the interface is reduced after the anodic oxidation as obtained from capacitance–voltage and photoluminescence measurements.     

Studies on the growth of CdTe on Si using ge interfacial layer in an organometallic vapor phase epitaxial system

Epitaxial CdTe layers were grown using organometallic vapor phase epitaxy on Si substrates with a Ge buffer layer. Ge layer was grown in the same reactor using germane gas and the reaction of germane gas with the native Si surface is studied in detail at low temperature. It is shown that germane gas can be used to “clean” the Si surface oxide prior to CdTe growth by first reducing the thin native oxide that may be present on Si. When Ge layer was grown on Si using germane gas, an induction period was observed before the continuous layer of Ge growth starts. This induction period is a function of the thickness of the native oxide present on Si and possible reasons for this behavior are outlined. Secondary ion mass spectrometry (SIMS) data show negligible outdiffusion and cross contamination of Ge in CdTe.     

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

We demonstrate epitaxially grown high-quality pure germanium (Ge) on bulk silicon (Si) substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD) without involving growth of thick relaxed SiGe buffer layers. The Ge layer is grown on thin compressively strained SiGe layers with rapidly varying Ge mole fraction on Si substrates resulting in several SiGe interfaces between the Si substrate and the pure Ge layer at the surface. The presence of such interfaces between the Si substrate and the Ge layer results in blocking threading dislocation defects, leading to a defect-free pure Ge epitaxial layer on the top. Results from various material characterization techniques on these grown films are shown. In addition, capacitance-voltage (CV) measurements of metal-oxide-semiconductor (MOS) capacitors fabricated on this structure are also presented, showing that the grown structure is ideal for high-mobility metal-oxide-semiconductor field-effect transistor applications.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Photonic effects during low-temperature ultraviolet-assisted oxidation of SiGe

The behavior of Ge atoms during dry oxidation of Si_0.8Ge_0.2 films at 300°C under 10 mbar of oxygen induced by vacuum-ultraviolet (VUV) illumination from an array of Xe₂* excimer lamps (λ=172 nm) has been studied. During VUV oxidation, samples are exposed to both a high concentration of ozone and atomic oxygen and a large flux of energetic photons. X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared (FTIR) spectroscopy investigations showed that the layers grown for shorter periods of time contain mostly SiO₂ with a few percent GeO₂. Most of the Ge atoms, initially present uniformly within the SiGe layer, were segregated and accumulated at the interface between the grown oxide and remaining SiGe. Angle-resolved XPS showed that the amount of GeO₂ within the grown oxide layer decreased for longer irradiation times and was located adjacent to the SiGe layer. When the grown SiO₂ layer reached a thickness around ～70 Å and the amount of Ge that had accumulated in the segregated layer more than doubled, a sharp increase in the Ge oxidation rate was observed. Continuing the oxidation for longer irradiation times resulted in the formation of a mixed oxide layer. The Ge segregation was not previously observed during other low-temperature oxidation treatments, including ozone-assisted oxidation, which provides the same oxidation species as VUV-assisted oxidation and similar growth rates. It is, therefore, concluded that a VUV photon-irradiation enhancement effect on Si and Ge interdiffusion has been introduced, possibly involving either Si-Si or Si-Ge bond softening or even breaking.     

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described.     

Special features of the formation of Ge(Si) islands on the relaxed Si1−xGex/Si(001) buffer layers

The results of studying the growth of self-assembled Ge(Si) islands on relaxed Si_1?xGe_x/Si(001) buffer layers (x≈25%), with a low surface roughness are reported. It is shown that the growth of self-assembled islands on the buffer SiGe layers is qualitatively similar to the growth of islands on the Si (001) surface. It is found that a variation in the surface morphology (the transition from dome-to hut-shaped islands) in the case of island growth on the relaxed SiGe buffer layers occurs at a higher temperature than for the Ge(Si)/Si(001) islands. This effect can be caused by both a lesser mismatch between the crystal lattices of an island and the buffer layer and a somewhat higher surface density of islands, when they are grown on an SiGe buffer layer.     

Epitaxial, high-K dielectrics on silicon: the example of praseodymium oxide

We show the first results for crystalline growth of praseodymium oxide on Si as a potential high-K dielectric with very promising electrical properties. All layer growth experiments were performed using solid source molecular beam epitaxy. The initial growth phase was studied using scanning tunneling microscopy. On Si(0 0 1) oriented surfaces, crystalline Pr₂O₃ grows as (1 1 0)-domains, with two orthogonal in-plane orientations. Epitaxial silicon overgrowth seems to be impossible. We obtain perfect epitaxial growth on Si(1 1 1). These layers can also be overgrown epitaxially with silicon. Finally, we show that the structural quality of epitaxial grown Pr₂O₃ on Si(0 0 1) degrades when the film is exposed to air due to silicon oxide formation at the interface based on oxygen indiffusion. However, it can be stabilized by capping with Si.     

Use of seed layers for structure,optical, and electronic transport measurements on microcrystalline silicon on glass

A detailed structural analysis is provided by which the benefits of thin undoped ‘seed layers’ for the preparation of microcrystalline silicon on glass for material characterization are demonstrated. Raman spectroscopy and photothermal deflection spectroscopy (PDS) results reveal that ‘seed layers’ are not only effective for the growth of structurally homogenous films and for an extension of the range of deposition parameters in which highly crystalline material is grown, but also allow for preparing material on glass with properties very close to that of functional layers in thin film solar cells. Films which have successfully been tailored in this way are characterized with respect to electrical conductivity and optical absorption. Regarding conductivity, hydrogenated microcrystalline silicon material grown on a ‘seed layer’ exhibits a structure‐dependent behaviour which is very similar to that observed for material grown on bare glass. Regarding optical absorption spectra, residual interference fringes, which indicate structural non‐uniformities, can be successfully removed by means of ‘seed layers’. As a result, more information is obtainable from PDS, and the data gained in this way are in good agreement with Raman spectroscopy results. Copyright © 2011 John Wiley & Sons, Ltd.     

Structural analyses of seeded thin film microcrystalline silicon solar cell

This contribution investigates the effect of seeding the growth of thin film microcrystalline silicon (µc‐Si : H) deposited by radio frequency plasma‐enhanced chemical vapor deposition on the material properties of µc‐Si : H film and the device performance of p‐i‐n and n‐i‐p µc‐Si : H solar cells. By means of Raman measurement, x‐ray diffraction (XRD) and transmission electron microscopy (TEM), we investigate the structure of seeded µc‐Si : H. In particular, the effect of seed layers on the crystallinity development is investigated. Measurements of the depth profile of the crystalline mass fraction using Raman spectroscopy show that seed layers lead to a more rapid and uniform crystallinity development in growth direction. The amorphous incubation layer is suppressed and crystallization begins directly from onset of film growth without evolving through the intermediate growth phases. From TEM analyses, we observe that crystal sizes are not affected by seed layers. Horizontal cracks are however observed to dominate the early growth of µc‐Si : H in p‐i‐n solar cell and this is reduced upon seeding. For the n‐i‐p cells, these cracks are not affected by seeding. XRD results also indicate that the use of seed layers does not affect the crystal sizes but affects the direction of preferential orientation. Solar cell external parameters show that seeding of p‐i‐n solar cells leads mainly to increase in short‐circuit current density, J_sc with a slight drop in open‐circuit voltage, V_oc. For the n‐i‐p cells, a reverse effect is observed. In this case, the V_oc increases and the J_sc decreases. Copyright © 2012 John Wiley & Sons, Ltd.     

Material Characterization of Ge1−x Sn x Alloys Grown by a Commercial CVD System for Optoelectronic Device Applications

High-quality compressive-strained Ge_1?x Sn _x /Ge films have been deposited on Si(001) substrate using a mainstream commercial chemical vapor deposition reactor. The growth temperature was kept below 450°C to be compatible with Si complementary metal–oxide–semiconductor processes. Germanium tin (Ge_1?x Sn _x ) layers were grown with different Sn composition ranging from 0.9% to 7%. Material characterizations, such as secondary-ion mass spectrometry, Rutherford backscattering spectrometry, and x-ray diffraction analysis, show stable Sn incorporation in the Ge lattice. Comparison of the Sn mole fractions obtained using these methods shows that the bowing factor of 0.166 nm (in Vegard’s law) is in close agreement with other experimental data. High-resolution transmission electron microscopy and atomic force microscopy results show that the films have started to relax through the formation of misfit and threading dislocations. Raman spectroscopy, ellipsometry, and photoluminescence (PL) techniques are used to study the structural and optical properties of the films. Room-temperature PL of the films shows that 7% Sn incorporation in the Ge lattice results in a decrease in the direct bandgap of Ge from 0.8 eV to 0.56 eV.     

A Vapor–Liquid–Solid Mechanism for Growing 3C‐SiC Single‐Domain Layers on 6H‐SiC(0001)

Growing device‐quality 3C‐SiC monocrystalline material is still an issue despite two decades of work dedicated to the subject. Using silicon as the substrate generates too many defects in the layers, owing to lattice mismatch, while it is very difficult to control the initial nucleation on an α‐SiC substrate so that 60° rotated domains are randomly formed. Herein, the elaboration of mono‐orientated 3C‐SiC layers on a 6H‐SiC(0001) on‐axis, Si face substrate using a vapor–liquid–solid mechanism is reported. This non‐conventional approach for growing monocrystalline layers involves feeding a Ge–Si melt by a propane flux at a temperature ranging from 1250 to 1550 °C. We show that, by using this technique, the 3C‐SiC material is almost always obtained on an hexagonal substrate, even if the crystal seed is oriented 8° off‐axis. Using on‐axis 6H‐SiC seeds and optimal growth conditions results in the reproducible deposition of single‐domain 3C‐SiC layers. A mechanism is proposed to clarify some aspects of this process.     

The influence of hydrogen and nitrogen on the formation of Si nanoclusters embedded in sub-stoichiometric silicon oxide layers

This work reports the study concerning the influence of the preparation conditions on the structure of silicon rich oxide (SRO) deposited by PECVD method by which the structural properties of the film are strictly related. In particular we investigated the role of reactant gases N₂O and SiH₄ on the total Si concentration, Si excess concentration, Si clustered concentration and size of nanoclusters formed by high annealing temperature. We payed particular attention on the role of the hydrogen and nitrogen during the Si agglomeration.The presence of hydrogen atoms on the as-deposited specimen, confirmed by the Si–H bonds peak on the FTIR analysis, has been directly correlated to the silicon excess concentration in the layer. The silicon, oxygen and nitrogen atomic density has been calculated from RBS analysis. These information were coupled to the ones obtained using methodology based on electron energy loss spectroscopy combined with energy filtered images, which allowed us to quantify the clustered silicon concentration in annealed sub-stoichiometric silicon oxide layers (SiO_x). We have verified that the nitrogen dissolved in the layer inhibits the Si excess clustering so that the efficiency of silicon agglomeration process decreases as the nitrogen content increases.