合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法,它综合了top-down和bottom-up两种时钟树拓扑产生方法,以最小时钟延时和总线长为目标,并把合理偏差应用到时钟树的构造中.电路测试结果证明,与零偏差算法比较,该算法有效地减小了时钟树的总体线长,并且优化了时钟树的性能.     

一种非零偏差时钟网布线算法

特定的非零偏差时钟网比零偏差时钟网更具优势,它有助于提高时钟频率、降低偏差的敏感度.文章提出了一种新的非零偏差时钟树布线算法,它结合时钟节点延时和时钟汇点位置,得到一个最大节点延时次序合并策略,使时钟树连线长度变小.实验结果显示,这种算法与典型的最邻近选择合并策略相比较,可以减少20%～30%的总连线长度.     

一种有效的变线宽时钟布线算法

针对时钟布线提出了一种有效的变线宽算法。该算法通过对时钟树中各树枝延迟敏感度的分析,选择总体最优的连线进行变线宽处理,使得时钟树的路径延迟最小化。在延迟优化后,为了使时钟偏差小于给定的约束,通过变线宽对各种钟汇点的延迟进行全面的再分配,使延迟最大的时钟汇点延迟最小化,而延迟较小的路径延迟适当增加,以进一步改善时钟树延迟。实验结果表明,该算法有较高的运行效率,时钟树的路径路径和时钟偏差得到了显著的改     

一种多级的零偏差时钟布线

时钟布线是设计高性能ＶＬＳＩ系统的重要一环。本文提出了一种新的多级零偏差时钟布线算法。首先，我们提出了一种基于加权选择的单级时钟树生成算法，在该算法中，基于均衡原则，对各种时钟汇点的负载电容，各时钟子树的延迟时间以及它们根节点之间的距离进行了综合考虑。     

时钟延时及偏差最小化的缓冲器插入新算法

本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小.     

一种加载缓冲器的有界偏差平面时钟布线算法

提出了一种加载缓冲器的有界偏差平面时钟布线方法.该方法由两步组成:第一步,由平面时钟布线生成一个时延相对平衡的平面时钟树;第二步,通过在平面时钟树的适当位置插入缓冲器,得到一个有界时钟偏差的平面时钟树.     

一种改进型FBT时钟树结构

针对混合型鱼骨平衡树(FBT)时钟结构的优缺点,结合宏单元的特性,提出了一种针对触发器与宏单元共存的改进型FBT时钟树结构,并总结出一种快速实现该时钟树的方法。在相同条件下,采用该方法实现的时钟树结构与二叉树型、鱼骨型时钟结构和传统的FBT时钟树结构进行比较,结果显示:鱼骨型时钟结构的时序质量最差;改进型FBT时钟树比二叉树型时钟树减少了15%的时钟延时和35%的时钟偏差,且整个过程的实现时间是传统FBT时钟树的30%。     

基于Astro的时钟树综合

时钟树综合是芯片后端设计至关重要的一环,时钟偏差成为限制系统时钟频率的主要因素。本文以一款TSMC0．25μm工艺的RISC微处理器芯片为例．介绍了使用Synopsys公司的P8LR工具Astro进行时钟树综合和优化的方法,并与Silicon Ensemble在综合后的时钟偏差上作了对比,结果显示使用前者比后者时钟偏差减小百分之十四以上。     

一种VLSI零偏差时钟线网布线算法

本文给出了一种时钟线网布线的新算法。算法基本上消化了时钟偏差，并使线网总线长得到了最小化。其关键在于：１在旋转定位的基础上，采用平衡合并的原则构造时钟树拓扑结构，并在合并过程中，保证点与弧之间的连续优化。２根据拓扑表，确定详细布线时的连线走向，从而对总线长作出了进一步的优化。实验结果表明，我们的算法是有效的，能够较好地用一大规模集成电路的时钟线网的布线。     

一种有效的VLSI平面时钟布线算法

本文提出了一种有效的VLSI平面时钟布线算法，通过自顶向下的对时钟汇点交替的进行水平和垂直划分，然后自底向上的沿着切割线方向对两棵子树进行合并来构造一棵平面时钟树，在构造时钟树的同时完成线网的连接。最后采用启发式的障碍避免算法使线网绕开障碍物。     

带偏差约束的时钟线网的拓扑构造和优化

提出了一种新的拓扑构造和优化方法,综合考虑了几种拓扑构造方法的优点,总体考虑偏差约束,局部进行线长优化.实验结果表明,它可以有效控制节点之间的偏差,同时保证减小时钟布线树的整体线长.     

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

As IC fabrication technologies get into nanometer era, clock routing gradually dominates chip performance indicated by delay, cost, and power consumption. X-architecture can be applied for routing metal wires in diagonal and rectilinear directions to overcome the above challenges due to wirelength reduction. In this paper, we present a clock routing algorithm, called PMXF, to construct an X-architecture zero-skew clock tree with minimum delay. An X-pattern library is defined for simplifying the merging procedure of the DME approach, an X-Flip technique is proposed for reducing the wirelength between the paired points, and a wire sizing technique is applied for achieving zero skew. In terms of clock delay, wirelength, power consumption, and via count listed in the experimental results on benchmarks, the proposed PMXF algorithm can respectively achieve more reductions compared with other previous X-architecture clock routing algorithms.     

一种层次式加载BUFFER的时钟网布线

多级时钟树构造是解决时钟布线问题的关键。本文提出一种新的层次式布线策略,它将拓扑生成,绕障碍ＤＭＥ及ＢＵＦＦＥＲ定位同时进行考虑,避免了布线的盲目性,减少了后处理工作。首先,对时钟汇点进行层次式均匀划分,在各个局域区域同时进行时钟子树的拓扑生成和ＤＭＥ嵌入;     

Legitimate Skew Clock Routing with Buffer Insertion

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective. Xinjie Wei received his B.Sc. degree in Computer Science from the PLA Nanjing Institute of Communications Engineering in 1993, and got M.S. degree in Computer Science from Xidian University in 1998. He is currently pursuing the Ph.D. degree at Tsinghua University. His research interests include computer network security, neural network and design automation for VLSI circuits and systems. And the major research attention is focused on VLSI physical design. Yici Cai received BSc degree in Electronic Engineering from Tsinghua University in 1983 and received in and MS degree in Computer Science & Technology from Tsinghua University in 1986, She has been an associate professor in the Department of Computer Science & Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout theory and algorithms. Meng Zhao has been an researcher in Semiconductor Industry Association of Beijing. She received her Bachelor of Engineering degree in Electronical Engineering from Tsinghua University, China, in 2000. She received her Master of Science degree in Computer Science from Tsinghua University, China, in 2003. Her research interests include VLSI design and CAD, Electronical material and device, VLSI verification and so on. Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the fellow of IEEE and the Senior Member of Chinese Institute of Electronics.     

用分量匹配法实现对高速时钟电路的动态优化

本文讨论如何设计工作在GHz频率下的VLSI芯片时钟电路.时钟树采用平衡平面布局消除时钟偏差;利用插入缓冲器对电路性能进行动态优化.最后用一个电路模拟软件对电路进行评估.和以往的工作相比较,本文实现了在频域内对时钟电路的优化,显著地提高了仿真速度.     

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

As technology advances into nanometer territory, clock network layout plays an increasingly important role in determining circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process variation. To alleviate the challenges to the existing routing algorithms due to the continuous increase of the problem size and the high-performance requirement, X-architecture has been proposed and applied to routing in that it can reduce wirelength and via counts, and thus improves the performance and routability compared with the conventional Manhattan routing. In this paper, we investigate zero skew clock routing using X-architecture based on an improved greedy matching algorithm (GMZSTX). The fitted Elmore delay model is employed to improve the accuracy over the Elmore delay model. The interactions among distance, delay balance and load balance are analyzed. Based on this analysis, an effective and efficient greedy matching scheme is suggested to reduce wire snaking and to get a more balanced clock tree. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that our algorithm (GMZSTX) achieves a reduction of 8.15% in total wirelength, 30.19% in delay and 55.31% in CPU time on average compared with zero skew clock routing in the Manhattan plane (BB+DME-2, which means using the top-down balanced bipartition (BB) method [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II—Analog & Digital Signal Process 39 (11) (1992) 799–814] to generate the tree topology and using the Deferred-Merge Embedding (DME) algorithm [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II—Analog & Digital Signal Process 39 (11) (1992) 799–814] to embed the internal nodes), and reduces delay and CPU time by 17.44% and 62.21% on average over the BB+DME-4 method (which is similar to BB+DME-2, but routing in X-architecture). Our SPICE simulation further verifies the correctness of the resulting clock tree.     

On general zero-skew clock net construction

We propose a simulated annealing based zero-skew clock net construction algorithm that works in any routing spaces, from Manhattan to Euclidean, with the added flexibility of optimizing either the wire length or the propagation delay. We first devise an O(log n) tree grafting perturbation function to construct a zero-skew clock tree under the Elmore delay model. This tree grafting scheme is able to explore the entire solution space asymptotically. A Gauss-Seidel iteration procedure is then applied to optimize the Steiner point positions. Experimental results have shown that our algorithm can achieve substantial delay reduction and encouraging wire length minimization compared to previous works     

A buffer distribution algorithm for high-performance clock netoptimization

We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a “good” tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. Our experiments complement the theoretical results. (2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interconnection delay dominates the clock delay, buffer congestion might exist in a layout. Using many buffers in a small wiring area results in substantial interline crosstalks as well as wirability, when the elongation of the imbalanced subtrees is necessary. Placing buffers evenly (locally or globally) over the plane at the minimum impact on wire length increase helps avoid buffer congestion and results in less crosstalk between clock wires. Thus, an effective technique for buffer distribution is proposed. Experimental results verify the effectiveness of the proposed algorithms. (3) Finally, a postprocessing step constraining on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. The proposed algorithm has an important application in MCM clock net synthesis as well as VLSI clock net synthesis