Degradation of double-gate polycrystalline silicon TFTs due to hot carrier stress

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion, we demonstrate that severe degradation phenomena may occur at the back polysilicon interface depending on the back-gate voltage during stress. The nature of these phenomena becomes evident when the back-gate bias is such that the back interface is coupled or decoupled from the front gate electrical characteristics.     

Ultrathin nitride/oxide (N/O) gate dielectrics forp+-polysilicon gated PMOSFETs prepared by a combined remoteplasma enhanced CVD/thermal oxidation process

Ultrathin nitride-oxide (N/O~1.5/2.6 nm) dual layer gate dielectrics have been incorporated into PMOSFETs with boron-implanted polysilicon gates. Boron penetration is effectively suppressed by the top plasma-deposited nitride layer leading to improved short channel performance as compared to PMOSFETs with oxide dielectrics. In addition, improved interface characteristics and hot carrier degradation immunity are also demonstrated for the devices with the N/O dual layer gate dielectrics     

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

Impact of nonuniform graded dopant profile in polysilicon gate on gate leakage current

In a MOSFET, a nonuniform, graded vertical dopant profile in the polysilicon gate causes a potential drop at the polysilicon/oxide interface. In this paper, the effect of this potential drop on the gate leakage current has been evaluated for the first time. The extent of variations of this affected gate leakage current with gate oxide thickness, gate length, and gate and drain bias conditions have been assessed with device simulation for an nMOS at 0.13 /spl mu/m low-voltage process. The results provide a guideline to the severity of this effect from the point of view of device and circuit operation and standby power consumption.     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.     

Threshold voltage, field effect mobility, and gate-to-channelcapacitance in polysilicon TFTs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V_t allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C_gc-V_GS characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C_gc characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C_gc curve can be related to the effective carrier transit time determined using the V_GS dependent field effect mobility     

On the electrical monitor for device degradation in the CHISEL stress regime

This paper reports a complete characterization of hot carrier-induced degradation in the CHannel Initiated Secondary ELectron (CHISEL) regime covering a large set of different stress bias conditions. Using several physical and electrical parameters, our results demonstrate that in the CHISEL regime, differently from the channel hot electrons case, the device degradation is univocally related to the gate current independently of the drain, source, substrate bias, and of the oxide electric field. The gate current is thus identified as the electrical monitor for device degradation in the CHISEL stress conditions.     

Influence of gate oxide breakdown on MOSFET device operation

The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.     

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N⁺ polysilicon gate device with highly doped Si layer, an asymmetrical P⁺/N⁺ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P⁺/N⁺ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.     

A self-consistent pseudo-two-dimensional model for hot-electron current in MOST' s

A theoretical formulation for the hot-electron currents (substrate and gate currents) in MOST's with nonuniform impurity profile has been built. By applying a gradual channel approximation for the source section and a pseudo-two-dimensional approximation for the drain section, saturation voltage is obtained by considering the voltage and channel current continuity at the boundary of the two sections. Three fitting parameters in the model are determined by comparing the theoretical calculation results with the observed substrate current in samples with various device parameters. The present model was successfully applied to describe the two experimental results: the gate oxide thickness dependence of the gate current injection efficiency and the kink in the maximum channel electric field strength versus gate voltage (= drain voltage) relation. The nonuniform channel impurity profile is approximated by the modified Gaussian distribution, which is found to agree well with the estimation by the substrate bias effect of MOST's. The calculated gate currents for the device can well explain the implantation energy dependence of the measured gate currents.     

Unified characterization of two-region gate bias stress insubmicrometer p-channel MOSFETs

P-channel MOSFETs stressed at a given drain voltage over the entire range of device saturation, 0 V⩽|V_G|⩽|V_D |, are discussed. Two different gate currents of opposite polarity were observed. These gate currents are shown to be correlated with device degradation behavior, which is distinctly different in each case. The gate bias thus divides into two stress regions, corresponding to small and large |V_G|. In the former, the parameter shift is initially pronounced but saturates in time. In the latter, the device degradation is initially small but cumulative in time. Therefore, both stress regions are equally important in affecting the device lifetime. A phenomenological model of gate current to support the two-region gate stress model is presented     

复合多晶硅栅LDMOS的设计

提出了一种应用于射频领域的复合多晶硅栅LDMOS结构,并提出了具体的工艺实现方法。此结构采用栅工程的概念,设计的栅由S-gate和D-gate两块并列组成,S-gate用高功函数P型多晶硅材料,D-gate用低功函数N型多晶硅材料。MEDICI模拟结果表明,该结构能够降低沟道末端和漏极附近的最高电场强度,提高器件的跨导和截止频率;同时,还能够提高器件的击穿电压,并减小器件的热载流子效应。     

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I_sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I_sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I_sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.     

Analysis and minimization of small-geometry effects on the currentgain of self-aligned `etched-polysilicon' emitter bipolar transistors

The authors report on a detailed analysis of small-geometry effects on the current gain of advanced self-aligned etched-polysilicon emitter bipolar transistors. By studying the dependence of collector and base currents on device geometry and process parameters, they have been able to identify the critical fabrication steps and physical mechanisms involved. The narrow emitter effect is caused by the butting of the emitter-base junction to the field oxide, and is mainly controlled by the gate oxide removal step prior to polysilicon deposition. Short emitter effects are associated with phenomena taking place in the spacer region of the device perimeter during polysilicon patterning, spacer pedestal thermal oxidation, link base implantation, and final rapid thermal anneal. Proper adjustment of all process parameters is shown to allow good control of the narrow-emitter effect and complete compensation of short-emitter effects, showing promise for the future of this CMOS-compatible bipolar transistor structure     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study n- and pMOS devices with 3.2–30 nm thick SiON or SiO₂ gate dielectrics and n⁺⁺ or p⁺⁺ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p⁺⁺ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n⁺⁺ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created.     

MOSFET parameter degradation after Fowler–Nordheim injection stress

We have investigated the degradation of tunnel oxides due to Fowler–Nordheim electron injection from polysilicon gate. Tested devices are n-MOSFET normally used for Flash EPROM applications with four different technologies for the tunnel oxide layer. Stresses have been performed at different source and drain bias conditions for a total injected charge up to 1 C/cm². The oxide characteristics and degradation have been determined comparing the MOSFET threshold voltage and transconductance peak for as received devices and after each stress step.