Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI

Redundancy of both logic circuits and interconnections is the core principle of both RVLSI (Restructurable or Fault-Tolerant VLSI) and WSI (Wafer Scale Integration). For varying complexity and sizes of circuits different factors of redundancy are required. Effective use of redundancy requires understanding of the failures and failure modes at different stages of the processing and lifetime of VLSI and WSI circuits. This paper consists of two parts. In Part I, sources of failures for MOS devices are discussed. Manifestations of physical failures are described. Use of redundancy for the yield improvement of VLSI circuits is explored through the use of a mathematical model. It is shown that interconnection density and pattern complexities around each section determines the effectiveness of yield improvement. In Part II (to be published in a forthcoming issue), programmable interconnect technologies are described to facilitate restructuring of VLSI and WSI circuits, in this case as they apply to yield improvement through the use of redundancy.     

Design of reconfigurable fault-tolerant VLSI/WSI processor array structures

This paper presents a new reconfiguration technique for VLSI/WSI processor arrays. The fault-tolerant capabilities of both interstitial redundancy and time redundancy are combined to provide optimal reconfiguration. Results obtained through Monte Carlo simulations show that with the proposed reconfiguration technique, a very high yield and chip area utilization is achieved. It is also shown that in the presence of harsh environments, where a high rate of transient faults occur, the proposed algorithm is more robust compared to the existing approaches.     

Reliable and fast reconfigurable hierarchical interconnectionnetworks for linear WSI arrays

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Θ(log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated     

Fault tolerance in FFT arrays: Time redundancy approaches

Fault tolerance in VLSI/WSI FFT arrays acquires relevance when defects and run-time faults become significant, due to large dimensions of processors and arrays. Then, both restructuring to overcome end-of-production defects and reconfiguration to overcome run-time faults are required, to achieve the dual purposes of higher yield and higher reliability.Adopting as basic FFT network the two-dimensions array that directly corresponds to the FFT flow graph, the usual structure redundancy techniques tailored for two-dimensions arrays reconfiguration are not well applicable, since the limited locality of this network leads to relevant area increase due to the augmented interconnection structure.In this paper,time redundancy is suggested as a viable alternative for the two-dimensions FFT array; two different solutions are presented, one based oninter-stage reconfiguration, the other one adoptingintra-state reconfiguration, both allowing for survival to multiple faults with limited increase of network complexity and very small hard-core sections. As usual in many time redundancy methods, both approaches result in a processing speed equal to half the processing speed granted by an ideal, fault-free device.Reliability and survival ratios to multiple faults are evaluated for the two cases, taking into account also the area increments necessary for fault tolerance. The reliability evaluations allow for a direct comparison of the two solutions.     

基于神经网络的单通道冗余VLSI/WSI阵列重构算法

本文提出了一个基于Hopfield网络的单通道冗余VLSI/WSI阵列重构算法,根据阵列中缺陷单元的分布情况,构造相应的矛盾图模型,将阵列的重构问题转化为求矛盾图的独立集且使得独立集的顶点数恰为缺陷单元的个数,有效地解决了阵列的重构问题.实验结果表明,与传统的启发式方法相比,基于本文所提出的图论模型而采用的神经网络方法是一种简单、快速、高效的算法.     

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO2phase-reversal zone plate lenses.     

Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques.     

ATM switching architectures for wafer-scale integration

This paper proposes the use of wafer-scale integration (WSI) technology for ATM switching systems and presents two different switching architectures specifically designed for WSI. WSI is particularly useful for switching networks since the interconnection lengths are minimized when the entire network is laid out on a single semiconductor wafer. We propose a defect-tolerant multipath buffered crossbar (MBC) with an expandable structure which can easily be scaled up or down according to the choice of wafer size. We also design an ATM-based Manhattan-street network (MSN) as an alternative architecture, suitable for wafer-scale implementation. We compare the two architectures from different standpoints such as performance, defect-tolerance, delay, practicality, testability, complexity, yield, and area     

WSI Polycide工艺的研究

文章基于0.5μm CMOS工艺,研究了造成Polycide工艺中WSI剥落、色斑等异常现象的原因。同时,研究了WSI淀积前清洗、退火温度及Cap Layer层对WSI薄膜翘曲度及应力的影响,并通过实验优化,以大量的数据为依据,对影响WSI薄膜特性的工艺参数进行调试和论证,主要考察更改各条件对圆片翘曲度及应力的变化,并通过显微镜镜检圆片表面,获得了0.5μm Polycide工艺较优的工艺条件。实验结果表明,在WSI淀积后增加Cap Layer层工艺对Polycide工艺工期WSI剥落、色斑等异常有较好的改善作用,且圆片表面形貌能达到MOS器件的工艺制造要求。     

Hybrid graph-based networks for multiprocessing

This article summarizes various ways of constructing large interconnection networks by performing different graph operations on smaller networks. The resultant hybrid graphs are classified, their inherent static topological properties are outlined and their relative advantages for multiprocessing applications are illustrated with several well-known networks. One class of hybrid graphs defined as compound networks, popularly known by an alternative name as hierarchical networks, is observed to be suitable for multicomputers in the current VLSI/WSI environment, as their use reduces network complexity, enhances scalability, reliability and fault-tolerance and supports locality of reference. This revised version was published online in June 2006 with corrections to the Cover Date.     

WASP: A WSI Associative String Processor

ASP (Associative String Processor) modules (and support software) comprise highly-versatile and fault-tolerant building-blocks for the simple construction of dynamically-reconfigurable low-MIMD/high-SIMD second-generation Massively Parallel Processor (MPP) systems. Indeed, based on state-of-the-art microelectronics and packaging technologies, ASP modules constitute a family of packaged MPP configurations for the cost-effective implementation of highly-compact application-specific high performance information processing systems.Based on scalar-vector content-matching rather than location addressing, ASP substrings comprise homogeneous fine-grain SIMD MPP structures, which, in operation, execute a form of set processing (i.e. a sequence of scalar-vector and vector-vector processes) on relevant data. Moreover, application flexibility enables simple tailoring of parallel processing power to match user requirements.WASP devices are WSI (Wafer Scale Integration) implementations of ASP substrings and, as such, constitute fundamental building blocks for the assembly of ASP modules. Exploiting either monolithic or hybrid 1 m CMOS WSI technologies, 8,192-processor WASP devices would enable the assembly of 65,536-processor SEM-E compatible ASP modules achieving 10 Tera-OPS/ft³, 1 Giga-OPS/W and 1 Mega-OPS/$ in cost-effectiveness.The paper discusses second-generation MPP design targets and describes ASP modules for real-time signal and data processing applications. In particular, the paper focuses on the architecture, operation, and implementation of the WASP device and reports on the progress of its development.     

Optical computing and interconnects

This paper discusses the present status of optical computing and interconnects, including device technology, and recent progress in three types of optical computing-analog, digital, and neural-is introduced. Examples of technologies used in an analog computing system, a technique for the optimal design of coherent phase-only spatial filters, and a new version of incoherent filtering are presented. The use of the modified sign digit number representation and its applications to digital optical computing are also described. Some architectures for optical neural computing are introduced, and the importance of optical interconnect technology in parallel computing is stressed. Permutation techniques, the board-to-board level interconnection techniques, and switching techniques are reviewed. Recent developments in optoelectronic devices and passive optical elements are outlined and finally some technological issues in optical computing and interconnects for practical use are discussed     

Integrated optoelectronic materials and circuits for optical interconnects

Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs Integrated Optoelectronic Circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC’s are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected.     

Future trends in wafer scale integration

The dramatic increase in the functional density of VLSI has been achieved without greatly increasing the chip size. In wafer scale integration, the area of an entire wafer is made available to increase the functional density still further. However, the requirement for fault tolerance, additional levels of metallization, excess power dissipation, process conservatism to achieve finite yield, and nonoptimum nature of the AI/SiO2transmission line for cross-wafer communication have made WSI noncompetitive with state-of-the-art VLSI and dense multichip hybrid packaging approaches, at least so far. On the other hand, the potential benefits of WSI are great. Chief among them is the greatly increased expected reliability, which is partly due to an all-monolithic system and partly because of the hope that fault tolerance, which is an absolute requirement for WSI fabrication, can be extended to failure tolerance, and thus the ability to reconfigure during systems operation, and perhaps even transparent to it. Pipeline- or bus-oriented logic structures were found to be the most promising for WSI implementation.     

Defect clustering viewed through generalized Poisson distribution

It is shown that generalized double Poisson distributions provide a good basis for yield models when moderate spatial heterogeneity exists between chips of larger sizes, or when defects are almost randomly distributed. The model includes the average number and size of clusters as its parameters. On being tested with simulated as well as actual wafer particle maps, the model gave a significance level >0.95 in most of the cases. This model is simple and facilitates direct implementation of multilevel or hierarchical redundancy in regular VLSI/WSI designs. The strength of the proposed model lies in its simplicity and its ability to provide a physical explanation of the clustering process through its parameters. The model reflects the effects of the competition which can occur among defects in a cluster during wafer processing. Comparisons of yield predictions by various models for wafer maps with different spatial properties are reported     

Introduction in space technologies, processing and applications of ULSI/WSI/3D-WSI on functional 3D nano- and optoelectronic elements

Dynamics and reforms by which the semiconductor industry could be transformed into next-generation manufacturing of Si and nano-electronic ULSI and WSI are discussed. For competitive Si ULSI and WSI the functional integration becomes a core design principle and cardinal simplification of manufacturing processes/equipment becomes a core technology principle. Concept of single-wafer single-lithography (no-lithography on spacefabs) technology for nano-electronic complementary bipolar field-effect (CBFE), Vertical Merged MOS (VMMOS) and optoelectronic VMMOS (OVMMOS), CBFE (OCBFE) elements increasing the packaging density for high-speed low-voltage ULSI and WSI is considered. Technology and Economics (Technonomics) concepts of space hyperhigh-vacuum technologies and processing in framework of flexible scalable no-lithography spacefab under condition of low and high orbital flight are presented.     

Model for yield and manufacturing prediction on VLSI designs foradvanced technologies, mixed circuitry, and memories

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP's and QFP's to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost     

芯片内/间无线互连技术发展综述

为了解决超大规模集成电路布线复杂的问题,无线互连技术(WIT)应运而生。介绍了实现芯片内/间无线互连的两类技术,一类是基于片上天线的无线互连技术,另一类是基于AC耦合的无线互连技术。从实现成本、功耗,传输性能方面对这两类技术进行了分析与比较,讨论了它们的具体应用及适用范围,同时也总结了两者目前存在的问题,并指出了其未来的研究方向,对今后芯片内/间无线互连技术的应用研究具有一定的参考意义。     

Breakthrough technologies for the high-performance electrical ATMswitching system

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The first step system was to use advanced Si-bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 μm bipolar SST technologies and Cu-polyimide multilayer MCM realized a 160 Gb/s throughput ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper first reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8×8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems