High-performance amorphous indium-gallium-zinc oxide thin-film transistors with polymer gate dielectric

The fabrication of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a spin-coated polymer gate dielectric on a glass substrate is reported. The interface state density at the poly(4-vinylphenol)/a-IGZO interface is only around 4.05 × 10¹¹ cm^− 2. The TFTs' threshold voltage, subthreshold swing, on-off current ratio, and carrier mobility are 2.6 V, 1.3 V/decade, 1 × 10⁵, and 21.8 cm²/V s, respectively. These characteristics indicate that the TFTs are suitable for use as nonvolatile memory devices and in flexible electronic applications.     

Organic thin film transistors with polymer high-k dielectric insulator

With the soluble copolymer poly(vinylidene fluoride–trifluoroethylene) (P(VDF–TrFE)) for the dielectric layer, we fabricate organic field effect transistors with enhanced gate effects, if we use P(VDF–TrFE) layers with a thickness of 2 μm. No hysteresis is observed. We obtain a relative dielectric constant of about 11 (at 1 kHz), which enables operation voltages smaller than for the organic insulator polymethylmetacrylate (PMMA, ε = 3.3 at 1 kHz). In contrast, for thinner films of P(VDF–TrFE) (250 nm), we find the typical ferroelectric hysteresis of the copolymer. This gives opportunities for building up organic transistors with a thin P(VDF–TrFE) ferroelectric layer as nonvolatile memory element.     

Role of high-k gate insulators for oxide thin film transistors

In conventional TFTs, SiO₂ or SiN_x have been used as gate insulators. But they could not induce the high on-current due to their low-capacitance. Since they have low-capacitance that originated from low dielectric constant, on-current of TFTs with low-k insulated are limited by low-capacitance. We have investigated high-k materials, such as HfO₂, ZrO₂ and modified structures for the use of gate insulators in oxide thin film transistors. ZrO₂ and HfO₂ are the most attractive materials with their superior properties, such as high breakdown field intensity (~ 15 MV/cm), high dielectric constant (~ 25), and the capability of room-temperature process. Since they have high-capacitance due to high dielectric constant, it can be easily expected to result in high on-current. In this work, we demonstrated the comparison of oxide thin film transistors with HfO₂, ZrO₂ and SiO₂ and the roles of gate insulators are analyzed. In the result, oxide thin film transistors with SiO₂, HfO₂ and ZrO₂ have on-currents of ~100 μA, ~500 μA, and ~3 mA, respectively. Especially oxide thin film transistor with ZrO₂ has larger on-current than oxide thin film transistor with HfO₂. The result means that ZrO₂ is more suitable than HfO₂ for the gate-dielectric material which can be fabricated at room temperature.     

High-performance carbon nanotube field effect transistors with a thin gate dielectric based on a self-assembled monolayer

Individual single-walled carbon nanotube (SWCNT) field effect transistors (FETs) with a 2 nm thick silane-based organic self-assembled monolayer (SAM) gate dielectric have been manufactured. The FETs exhibit a unique combination of excellent device performance parameters. In particular, they operate with a gate-source voltage of only -1 V and exhibit good saturation, large transconductance, and small hysteresis (相似文献   

Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

并五苯场效应晶体管的研制

以X射线衍射仪（XRD）研究了在硅表面形成并五苯多晶薄膜晶体结构，通过原子力显微镜（AFM）分析了在二氧化硅表面形成并五苯多晶薄膜的形貌。以热氧化的硅片作为绝缘栅极，并五苯作为有缘层，采用底接触结构，研制场效应晶体管。经过测试得到其场效应迁移率为1．23cm^2/Vs，开关电流比＞10^6。     

Electrical property of pentacene organic thin-film transistors with a complementary-gated structure

Organic thin-film transistors (OTFTs) are being extensively studied for the next generation electronic devices, which will require cost reduction and flexibility. In this study, OTFTs with a double-gated structure were fabricated and their electric properties depending on main and complementary gate voltages were presented. Not only the drain currents, but also the surface potentials of pentacene films were remarkably modulated in accordance with the complementary gate field. A pMOS d-inverter circuit constructed with conventional and double-gated OTFTs was designed and fabricated, and the gain of the d-inverter measured at V _CG = 0 V was approximately 2.8.     

Low-voltage organic field-effect transistors (OFETs) with solution-processed metal-oxide as gate dielectric

In this study, low-voltage copper phthalocyanine (CuPc)-based organic field-effect transistors (OFETs) are demonstrated utilizing solution-processed bilayer high-k metal-oxide (Al(2)O(y)/TiO(x)) as gate dielectric. The high-k metal-oxide bilayer is fabricated at low temperatures (< 200 °C) by a simple spin-coating technology and can be controlled as thin as 45 nm. The bilayer system exhibits a low leakage current density of less than 10(-5) A/cm(2) under bias voltage of 2 V, a very smooth surface with RMS of about 0.22 nm and an equivalent k value of 13.3. The obtained low-voltage CuPc based OFETs show high electric performance with high hole mobility of 0.06 cm(2)/(V s), threshold voltage of -0.5 V, on/off ration of 2 × 10(3) and a very small subthreshold slope of 160 mV/dec when operated at -1.5 V. Our study demonstrates a simple and robust approach that could be used to achieve low-voltage operation with solution-processed technique.     

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V_GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10¹¹ cm^− 2, needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.     

Low-voltage-driven pentacene thin-film transistors with cross-linked poly(4-vinylphenol)/high-k Bi55b3O15 hybrid dielectric for phototransistor

This paper describes the fabrication of pentacene thin-film transistors (TFTs) with an organic/inorganic hybrid gate dielectric, consisting of cross-linked poly(4-vinylphenol) (PVP) and Bi5Nb3O15. A 300-nm-thick Bi5Nb3O15 dielectric film, grown at room temperature, exhibits a high dielectric constant (high-k) value of 40 but has an undesirable interface with organic semiconductors (OSC). To form better interfaces with OSC, a cross-linked PVP dielectric was stacked on the Bi5Nb3O15 dielectric. It is shown that, with the introduction of a hybrid dielectric, our devices not only can be operated at a low voltage (- -5 V) but also have improved electrical characteristics and photoresponse, including a field-effect mobility of 0.72 cm2/V x s, current sub-threshold slopes of 0.29 V/decade, and a photoresponse of 4.84 at a gate bias V(G) = 0 V under 100 mW/cm2 AM 1.5 illumination.     

Tungsten oxide as a gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Tungsten oxide is currently used as gate insulator in pH-sensing ion-sensitive field-effect transistors (ISFETs) and in electrochromic devices. Its great potential as a high-κ dielectric with high transparency and temperature stability is reported. Owing to the low gate voltage sweep necessary to turn the transistor on and off, a possible application could be as a low-voltage pixel driver in active-matrix displays in harsh environments.     

Analysis of threshold voltage shift of pentacene field effect transistor with ferroelectric gate insulator as a Maxwell-Wagner effect

The current-voltage (I-V) characteristics of pentacene filed effect transistor (FET) with ferroelectric gate insulator (P(VDF-TeFE)) is investigated to analyze the threshold voltage shift in terms of Maxwell-Wagner (MW) effect. The spontaneous polarization generated in ferroelectric gate insulator modulates the amount of accumulated charges which is injected from the source electrode, and causes threshold voltage shift. Two peaks observed in the I-V characteristics were analyzed based on a MW effect element. Results reveal that the movement of accumulated charges at the pentacene/P(VDF-TeFE) interface along the electric field in the FET, and the ferroelectric polarization of P(VDF-TeFE) are main origins of the peaks.     

Ambipolar field effect transistors with heterojunction of organic semiconductors

Ambipolar operations in organic field effect transistors (OFETs) with heterojunction structures have been demonstrated. We have selected a biphenyl capped thiophene oligomer (BP2T) as p-type and fullerene (C₆₀) as n-type materials in the active layer of the OFETs. To investigate their intrinsic behaviors we measured the OFET characteristics in vacuum without breaking vacuum after device fabrication. Their electric characteristics depended on the heterostructure configurations. The OFET prepared with a co-deposited thin film of BP2T/C₆₀ showed high carrier transport performance and both carriers were efficiently injected into the channel of the active layer. In the bi-layered device, ambipolar characteristics were only observed when the n-type C₆₀ molecules penetrated deeply into the BP2T layer.     

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.     

Memory effect of a polymer thin-film transistor with self-assembled gold nanoparticles in the gate dielectric

A self-assembled film of gold nanoparticles is integrated into the gate dielectric of an organic thin-film transistor to produce memory effects. The transistor is fabricated on a heavily doped n-type silicon (n/sup +/-Si) substrate with a thermally grown oxide layer of 100 nm thick. n/sup +/-Si serves as the gate electrode while the oxide layer functions as the gate dielectric. Gold nanoparticles as the floating gate for charge storage are deposited on the gate oxide by electrostatic layer-by-layer self-assembly method. A self-assembled multilayer of polyelectrolytes, together with a thin spin-coated poly(4-vinyl phenol) layer, covers the gold nanoparticles and separates them from the poly(3-hexyl thiophene) channel. Gold nanoparticles are charged or discharged with different gate bias so that the channel conductance is modulated. The memory transistor has an on/off ratio over 1500 and data retention time of about 200 s. The low-temperature solution-based process is especially suitable for plastic-based circuits. Therefore, the results of this study could accelerate achievement of cheap and flexible organic nonvolatile memories.     

Bootstrapped inverter using a pentacene thin-film transistor with a poly(methyl methacrylate) gate dielectric

A bootstrapped inverter incorporating pentacene organic thin-film transistors (OTFTs), with poly(methyl methacrylate) as the gate dielectric, has been designed, fabricated and tested. The inverter uses capacitive coupling and bootstrapping effects, and exhibits superior performance to the normal diode-connected load inverter. The pentacene OTFTs used for the inverter possess a field-effect mobility of 0.32 cm²/V/s, a threshold voltage of -10.0 V, a subthreshold slope of 1.5 V per decade and an on/off current ratio of 2.2 times 10⁶. The inverter has a 30 mus rise time and a 450 mus fall time, at an operating frequency of 1 kHz and 30 V drive voltage.     

Characterization of gold nanoparticle pentacene memory device with polymer dielectric layer

We report on the electrical behavior of gold nanoparticles (Au NPs) intervened metal-pentacene-insulator-semiconductor structures. The structure adopts polyvinyl alcohol (PVA) and pentacene as gate insulator and semiconductor, respectively. On the PVA (250 nm) film which was spin-coated and UV cross-linked, 3-aminopropyl triethoxysilane was functionalized for self assembling of the Au NPs monolayer. The devices exhibited clockwise hysteresis in their capacitance-voltage characteristics, with a memory window depending on the range of the voltage sweep. A relatively large memory window of about 4.7 V, which was deduced from control devices, was achieved with voltage sweep of (−/+)7 V. Formation of the monolayered Au NPs was confirmed by field effect scanning electron microscopy and atomic force microscopy.