SiC JFET功率特性的仿真与优化

建立了常关型SiC结型场效应晶体管(JFET)功率特性的数值模型,研究了不同的结构和材料参数对器件功率特性的影响。仿真结果显示,沟道层、漂移层等各层的厚度及掺杂浓度对器件的开态电阻和击穿电压都有明显的影响;采用电流增强层可以明显提高器件的功率特性。研究结果表明,对SiC JFET的结构参数进行优化,可以有效提高器件的优值(FOM)。     

基于共享Buffer的LIGBT和PLDMOS器件研究

介绍了基于共享Buffer技术的SOI(绝缘体上硅)LIGBT和PLDMOS,相对于传统工艺可以节约2层光刻板和2步工艺流程。主要通过研究在器件漏区的缓冲层特性,对器件特性影响明显。通过实验和仿真结果对比,共享Buffer技术的器件通过工艺和版图优化后能达到原有器件的表现性能。     

4H-SiC浮动结JBS器件的设计方法

研究了4H-SiC浮动结(FJ)结势垒肖特基(JBS)二极管的设计方法。提出在上外延层厚度一定的情况下得到外延层最佳掺杂浓度,然后以器件的功率优值(BFOM值)为依据确定出最佳下外延层厚度,进而设计出浮动结和表面结的最佳结构参数。否定了文献中认为浮动结位于器件中部为最佳设计的结论。仿真结果表明浮动结和表面结线宽比不仅影响器件导通特性,还会影响反向特性。浮动结线宽比在一定范围内会略微影响器件击穿电压,而表面结线宽比主要影响器件的反向泄漏电流。     

一种快速关断沟槽型SOI LDMOS器件

围绕降低沟槽型SOI LDMOS功率器件的优值,提出了一种新型多栅沟槽 SOI LDMOS器件(MG-TMOS)。与常规沟槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不牺牲击穿电压的同时,降低了器件开关切换时充放电的栅漏电荷和器件的比导通电阻。这是因为:1) 新型MG-TMOS器件沟槽里的保护栅将器件的栅漏电容转换为器件的栅源电容和漏源电容,大幅度降低了器件的栅漏电荷;2) 保护栅偏置电压的存在使得器件导通时会在沟槽底部形成一层低阻积累层,从而降低器件的导通电阻。仿真结果表明:该新型沟槽型SOI LDMOS器件的优值从常规器件的503.4 mΩ·nC下降到406.6 mΩ·nC,实现了器件的快速关断。     

一种改善VDMOSFET高频性能新结构的分析与研究

栅电荷是低压功率MOSFETs开关性能的一项很重要的参数。器件优值（Ron＊Qg）是常用来量化开关性能的指标。文中对传统结构和新结构的栅电荷特性进行了二维数值模拟,并推导出可用于计算栅电荷的解析模型。仿真结果表明新结构相对于常规结构,栅电荷降低42．93％,器件优值降低37．05％。最后对新结构进行了参数优化。     

MOS型功率器件

本文综述了现代MOS型功率器件的原理、发展及应用趋势。在此类器件所用的终端技术上,提出了一个优值作标准。此外,还介绍了频率与功率的极限关系,并指出了器件的发展方向。     

功率电子器件的现状和最新进展

本文概述了功率电子器件的现状,介绍了用于评估功率电子器件性能的两种优值(Figure of merit)和更广泛使用功率电子器件的SEES方案预测的节能效果。最后,以优值来评估最近研发的硅功率电子器件的新结构,包括S-J MOS、LDMOS、VDMOS、IGBT、BIGT和RF功率MOS等器件结构的改进与创新。     

功率VDMOS器件用硅外延材料研制

文章阐述了硅功率VDMOS器件的基本原理和器件结构,也展现了作为电力电子器件其广阔的应用领域,提出了功率VDMOS器件对硅外延材料的要求和发展方向。依据功率器件对外延片的要求,通过优化外延工艺程序和优化外延工艺参数,消除或减弱了自掺杂对电阻率均匀性的影响,消除了过渡区对厚度均匀性的影响,也较好地控制了外延层中的结构缺陷...     

高电流增益SiC BMFET功率特性的优化研究

研究了栅电流及结构参数对SiC双极模式场效应晶体管(BMFET)功率特性的影响。仿真研究的结果表明,SiC BMFET器件的开态电阻和电流增益都会随着栅电流的上升而显著下降。沟道掺杂浓度越低,沟道宽度越窄,双极模式调制器件开态电阻的效果越明显,但同时电流增益会降低。相比于单极模式SiC结型场效应晶体管(JFET),SiC BMFET可以显著提升器件的FOM优值,降低器件功率特性对结构参数的敏感度,同时降低了常关型器件的设计难度。     

抗SEB加固功率VDMOS的温度特性研究

仿真研究了300 V抗辐射功率VDMOS器件在不同缓冲层浓度、不同LET值下单粒子烧毁(SEB)效应的温度特性。结果表明,SEB的温度特性与LET值相关,LET值较小时(0.1 pC/μm),SEB电压呈正温度系数特性;LET值较大时(1 pC/μm),SEB电压呈负温度系数特性。重点分析了1 pC/μm LET时离化强度大的条件下SEB电压的碰撞电离分布和晶格温度分布,分析发现,功率VDMOS颈区JFET/P阱的pn结是SEB效应薄弱点,这得到了实验结果的验证。本模型计算的结果表明,当LET值大、器件工作温度高时,功率VDMOS器件的单粒子烧毁风险最大。该项研究结果为抗辐射加固功率VDMOS器件的应用提供技术参考。     

Power semiconductor device figure of merit for high-frequencyapplications

A figure of merit (the Baliga high-frequency figure of merit) is derived for power semiconductor devices operating in high-frequency circuits. Using this figure of merit, it is predicted that the power losses incurred in the power device will increase as the square root of the operating frequency and approximately in proportion to the output power. By relating the device power dissipation to the intrinsic material parameters, it is shown that the power loss can be reduced by using semiconductors with larger mobility and critical electric field for breakdown. Examination of data in the literature indicates that significant performance improvement can be achieved by replacing silicon with gallium arsenide, silicon carbide, or semiconducting diamond     

Improvement of the ON resistance of power VDMOS devices by surface doping: effect on the breakdown voltage

An efficient way to improve the ON resistance R_on of a vertical double-diffused MOS device is to implant a shallow, lightly doped layer over the drift area of the device. The evolution of R_on for different voltage handling capacities vs. (i) the junction depth and (ii) the concentration of this layer was studied. The figure of merit (the product of R_on and the surface area) of the device was calculated using an analytical unidimensional model and with a two-dimensional numerical simulator. The influence of this surface doping technique on the breakdown voltage of the device was investigated. Comparison between the analytical and numerical approaches shows that two-dimensional effects are important. The trade-off between the factor of merit and the breakdown voltage is emphasized and design rules to use the surface doping technique for devices with voltage handling capacities of 50, 150 and 400 V are given.     

An optically controlled SiC lateral power transistor based on SiC/SiCGe superjunction structure

An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 μm and 0.7 μm are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively.     

Guide lines for the selection of acoustooptic materials

Guide lines are presented for the selection of promising new acoustooptic materials for device applications. Previously, the selection of materials was based primarily on availability and intuition. Now it is possible to estimate an approximate acousto-optic figure of merit for a material knowing only its chemical composition and density. One of the first applications of these guide lines led to a detailed evaluation of lead molybdate, PbMoO4, a material known to have certain desirable physical properties. The results verified that PbMoO4has a high figure of merit, considerably greater than LiNbO3though somewhat less than α-HIO3. In addition to a high figure of merit, a material must also have a low acoustic loss if it is to be useful for device applications. The relationship between the acoustooptic figure of merit and acoustic loss is explored. Although only limited loss data are presently available, it is concluded that a high figure of merit and low loss are compatible material properties for applications below approximately 0.5 GHz. However, as future applications call for higher frequency operation, it appears that a tradeoff between low acoustic loss and high figure of merit will be required.     

Optimal Electrical Conductivity for Maximum Thermoelectric Figure of Merit

A frequently employed approach for determination of the maximum thermoelectric figure of merit of a material involves a calculation of its maximum electrical power factor and the corresponding thermal conductivity. In this study, we show that the thermoelectric figure of merit determined using this approach is likely to be limited by the Lorenz factor. The maximum thermoelectric figure of merit is achieved at a different electrical conductivity. A simple way of estimating the optimal electrical conductivity for obtaining the maximum thermoelectric figure of merit is presented.     

Maximally efficient gain: a figure of merit for linear active 2-ports

A new power/gain invariant is proposed as a high-frequency figure of merit for linear active 2-ports. Using this figure of merit, it is feasible to design amplifiers with potentially unstable devices which have power gains comparable in magnitude to Mason's U function and are optimum in the sense of maximising the 2-port added power.     

A figure of merit for a varactor-tuned microwave oscillator

This note derives a figure of merit for a varactor tuned microwave solid state oscillator. Thu figure of merit is in terms of electronic tuning range and power output normalized to the available power from the untuned oscillator. This enables the varactor which will give the required combination of thorns parameters to be specified in terms of y and f _c.

The figure of merit also shows that a varactor with a large value of the product yf _c maximizes the figure of merit.     

Global interconnect width and spacing optimization for latency, bandwidth and power dissipation

This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically.     

MOCVD-Grown AlGaN Buffer GaN HEMTs With V-Gates for Microwave Power Applications

We report the performance of AlGaN buffer GaN high-electron mobility transistors (HEMTs) grown by metal–organic chemical vapor deposition. GaN HEMTs on high-quality AlGaN buffer were grown on SiC substrates. The incorporation of an AlGaN buffer into the GaN HEMT significantly improves channel confinement and suppresses the short-channel effect. Advanced deep-recess V-gate structures were employed to optimize the device for better microwave power performance. With a 10-nm GaN channel layer sandwiched between the AlGaN barrier and buffer, excellent power performance was achieved. The output power density is 13.1 W/mm, and the associated power-added efficiency is 72% at 4-GHz frequency and 48-V drain bias. This power performance is comparable to the state-of-the-art GaN HEMTs grown on GaN buffers, indicating that the AlGaN buffer in our optimized device structure does not introduce any noticeable trapping.      

Ultrahigh-performance 8-GHz SiGe power HBT

This letter has demonstrated the state-of-the-art SiGe power heterojunction bipolar transistors (HBTs) operating at 8 GHz. In a common-base configuration, a continuous wave output power of 27.72 dBm with a concurrent power gain of 12.19 dB was measured at a peak power-added efficiency of 60.6% from a single SiGe HBT with a 3-/spl mu/m emitter finger stripe width and a 1340 /spl mu/m/sup 2/ total emitter area. The highest power-performance figure of merit (FOM) of 3.8/spl times/10/sup 5/ mW/spl middot/GHz/sup 2/ achieved from the device was resulted from using an optimized SiGe heterostructure and a compact device layout, which is made possible with a heavily doped base region.