点涂工艺技术研究

针对采用点涂工艺技术对焊膏、贴片胶常用电子组装工艺材料进行涂覆，主要从材料的选型、关键工艺参数设置方法以及点涂缺陷等几方面进行了分析，并且通过实际组装质量的相关检测，证明了点涂工艺技术的适用性，推荐了点涂技术中应优选的材料型号和工艺参数。     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

球形焊点三角形排列倒装芯片底部填充的能量法研究

对于具有球形焊点且呈正三角形排列的倒装芯片,由于其待填充的空隙结构复杂,难以通过平均毛细压来建立底部填充的解析模型.因此通过能量变化来分析底部填充过程以避免平均毛细压的计算.首先分析了底部填充过程中表面能的变化、动能的变化和流道壁面对流动的阻力损耗;然后根据能量守恒定律得到了反映底部填充过程的新解析模型;最后用计算流体力学(CFD)软件对底部填充过程进行了三维数值模拟,以此验证了基于能量法的新解析模型.能量法更具有通用性,可用于研究焊点形状和排列方式复杂的倒装芯片底部填充过程.     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

PoP叠层封装的组装工艺（下篇）

作者汇集国际会议相关外文论文,结合作者在华为等企业的工作实践,撰写此文,供同行参考。本文介绍了PoP（PackageonPackage）叠层封装的基本结构,SMTI艺模式和SMT组装工艺过程,重点介绍了PoP叠层封装的助焊剂／锡膏的浸蘸工艺过程,介绍了浸蘸锡膏材料及浸蘸锡膏的特性要求,PoP再流焊温度曲线的设定,对预制PoP和在板PoP热循环疲劳结果分析。从底部填充材料选择、填充空洞、底部填充可靠性3个方面介绍YPoP器件的底部填充效果和工艺。介绍To．4mm细间距PoP器件的SMT组装工艺过程,及相关工艺参数的设定。介绍了0．4mm穿透模塑通孔（TMV）结构PoP器件的空气气氛下的再流焊工艺过程及相关工艺参数的设定。从对焊接缺陷、PoP封装各层状况和翘曲测量方面来介绍如何进行PoP器件的×射线检测。从共面性和高温翘曲、温度循环、跌落冲击和弯曲疲劳4个方面介绍了0．4mmPoP器件的可靠性。本文最后介绍了PoP器件的清洗。     

底部填充工艺的瞬时温度环境管理

微电子组装的大部份工艺开发都要求将元件做到更小,以便在尺寸日益缩小的便携式设备上实现更多功能。阐述了大元件的底部填充,即一侧的尺寸超过15mm,底部填充的胶量介于30～50mg。大尺寸晶元的制造工艺要求比现有生产线更大的产能,这就给底部填充点胶带来更大的挑战。大元件的产能超过3000个/h时,需要点胶机点出非常多的胶水。如此多的胶水在出胶前通过点胶阀,这将会带来加热的问题-某些工艺要求出胶前胶水必须要加热。这会对胶点尺寸有影响,因为随着温度的变化,底部填充的胶水黏度也会随之变化,从而轻微影响点出的胶量。从而将影响晶元相邻的“非沾染区”。稳定的温度是点胶稳定性的保证,并且能帮助胶水流进晶元下方同时也有助胶水分离从而更容易喷射出来。从研究中可以观察到：系统温度环境（点胶机内部）对点胶的胶水质量有影响。     

陶瓷表面状态对底部填充胶流动性影响研究

由于陶瓷外壳表面会做氧化铝涂层,这种处理会对底部填充胶的扩散性能造成影响。研究了底部填充胶在不同表面状态的陶瓷外壳上的扩散状态。这对底部填充工艺的发展具有重要的意义。     

用热力学原理研究光纤光缆用填充胶的稳定性

光纤光缆用填充胶的最主要指标包括分油性、滴点、闪点三个，而这些指标均属于热力学指标。因此，为了能从理论上对上述三类指标的定量建立一个有效的理论模型，本文从填充胶体系的稳定性机理和途径、絮凝化机理和预防途径等方面进行了分析，并通过对于吸引、排斥、位阻三类位能的研究，总结出了光缆光纤填充胶体系稳定性的临界化条件，最后用实验进行了验证。     

PoP叠层封装的组装工艺（上篇）

作者汇集国际会议相关外文论文,结合作者在华为等企业的工作实践,撰写此文,供同行参考。本文介绍了PoP（Package on Package）叠层封装的基本结构,SMT工艺模式和SMT组装工艺过程,重点介绍了PoP叠层封装的助焊剂／锡膏的浸蘸工艺过程,介绍了浸蘸锡膏材料及浸蘸锡膏的特性要求,PoP再流焊温度曲线的设定,对预制PoP~O在板PoP热循环疲劳结果分析。从底部填充材料选择、填充空洞、底部填充可靠CtgE3个方面介绍了PoP器件的底部填充效果和工艺。介绍了0．4mm细间距PoP器件的sMT组装工艺过程,及相关工艺参数的设定。介绍了0．4mm穿透模塑通孔（TMV）结构PoP器件的空气气氛下的再流焊工艺过程及相关工艺参数的设定。从对焊接缺陷、PoP封装各层状况和翘曲测量方面来介绍如何进行PoP器件的X线检测。从共面性和高温翘曲、温度循环、跌落冲击和弯曲疲劳4个方面介绍了0．4mmPoP器件的可靠性。本文最后介绍了PoP器件的清洗。     

一种新型粘接胶在厚膜混合集成电路中的推广应用

本文对现用粘接胶存在的问题进行了阐述，针对该问题选择了4种新型粘接胶，通过对比试验优选出0145粘接胶，并进行可靠性研究。     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

A computational study on solder bump geometry, normal, restoring, and fillet forces during solder reflow in the presence of liquefied underfill

A computational survey was performed to evaluate the effect of volume and material properties on a concurrent underfilling and solder reflow manufacturing technique applied to flip-chip technology. Fillet geometry in addition to collapsed solder ball geometry and forces during solder reflow in the presence of liquefied underfill are reported. Targeted material properties included surface tension, wetting angles, and process parameters such as underfill volume. A regression model is presented representing over 1000 case studies completed using surface evolver. Also, a multiple ball model was developed to study the solder ball array behavior. Modeling results are presented. Application of this model for wafer applied coating underfill thickness prediction was also studied including the fillet forces added to a multiple-ball-model. Behavior and force studies combining all these effects were performed and are presented. Finally, a more realistic arrangement consisting of circular and square solder pad geometries combined is modeled for a single ball. The models results are expanded to include a multiball model employing a commonly used regression method. Solder joints were cross-sectioned and measured after reflow in the presence of a fluxing underfill for comparison to model predictions. The experimental results agree within 1.5%.     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Underfill of flip chip on organic substrate: viscosity, surface tension, and contact angle

In flip-chip packaging, an underfill is dispensed on one or two adjacent sides of the die. The underfill is driven by a capillary flow to fill the gap between the die and substrate. The application of an underfill reduces the stress to solder bumps and enhances the reliability of the solder joints. Underfill materials consist of epoxy or cyanate ester resins, catalyst, crosslinker, wetting agent, pigment, and fillers. Underfill materials are highly filled with the filler loading ranging from 40% to 70%. In terms of underfill material processing, fast flow and curing are desired for high throughput. The viscosity, surface tension, and contact angle are key material properties affecting the gap filling process. In order to achieve fast filling, it is required that an underfill material has low viscosity and low contact angle at dispensing temperatures. Due to curing of an underfill material at dispensing temperature, the viscosity increases with time, which complicates the underfill flow process. The rheological behavior of several underfill materials was experimentally studied. All the underfill materials showed strong temperature dependence in viscosity before the curing. The time dependent viscosity and curing of underfill materials were examined by a dynamic time sweep test. The effects of viscosity and curing behavior of underfill materials on underfill material processing were investigated. The material with a longer gel time had more stable viscosity at room temperature, and therefore longer pot life. Experimental methods were developed to measure the surface tension and the contact angle of underfills at temperatures over 100 °C. Results showed that the contact angle for underfill on a substrate was time dependent. The interaction between underfill and substrate affects not only gap filling, but also filleting. The effect of surface energies of flip-chip substrates on wetting angles was also studied. Experiment results showed that for the same underfill, the higher the surface energy of substrate, the better the filleting.     

底部填充工艺探讨

底部填充工艺是倒装芯片封装过程中的一个必不可少而且很关键的组成部分,底部填充工艺的成败将直接影响到封装的可靠性。本文针对底部填充工艺中需考虑的多个方面,如分配模式、胶水体积计算、硬件选择等,阐述如何改进工艺,增强底部填充的自动生产的能力。     

Recent advances in the development of no-flow underfillencapsulants-a practical approach towards the actual manufacturingapplication

No-flow underfill technology has been proven to have potential advantages over the conventional underfill technology, and a no-flow underfill material (called G25) has been developed and reported in our prior papers. In this paper, two modified no-flow underfill materials are studied. Compared to the G25 no-flow underfill material, these two materials can be fully post-cured at the temperature below 170°C. These two materials also exhibit lower coefficient of thermal expansion (CTE), lower moisture absorption, better adhesion, and more fluxing stability. In this study, a differential scanning calorimetry (DSC) is used to study the curing kinetics and glass transition temperature (DSC Tg) of the two materials. Thermo-mechanical analyzer (TMA) is used to investigate the heat distortion temperature (TMA Tg) and the coefficient of thermal expansion (CTE). Dynamic-mechanical analyzer (DMA) is used to measure the storage modulus (E') and loss modulus (E") within the temperature range from 25°C to 250°C and then estimate the cross-linking density (p) of the cured material system. Rheometer is used to investigate the material viscosity. Die shear testing is conducted to investigate the adhesive strength between the cured underfill material and polyimide passivation layer. Surface mount technology (SMT) reflow oven, quartz chips and copper laminated FR4 substrates are used to in-situ test the processability of the two materials. Scanning electron microscopy (SEM) is used to observe the integrity of the reflowed solder interconnects. A potential approach toward the production application of no-flow underfill material is then proposed     

Study of the fluxing agent effects on the properties of no-flowunderfill materials for flip-chip applications

As one of the key requirements of the no-flow underfill materials for flip-chip applications, a proper self-fluxing agent must be incorporated in the developed no-flow underfill materials to provide proper fluxing activity during the simultaneous solder reflow and underfill material curing. However, most fluxing agents have some adverse effects on the no-flow underfill material properties and assembly reliability. In this paper, we have extensively investigated the effects of the concentration of the selected fluxing agent on the material properties, interconnect integrity and assembly reliability. Through this work, an optimum concentration window of the fluxing agent is obtained and a routine procedure of evaluating fluxing agents is established     

Novel reworkable fluxing underfill for board-level assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.     

倒装芯片下填充流动二维化数值分析方法的应用

下填充流动是确保倒装芯片可靠性的重要封装工艺,其流场和流动过程具有明显的二维特征,通过降维得到的二维化数值分析新方法能高效地模拟下填充流动过程.针对一种焊球非均匀、非满布的典型倒装芯片,用该数值分析方法模拟了单边下填充流动的过程,并用实验对模拟结果进行了检验.实验采用了可视化的下填充流动装置,倒装芯片试样采用硅-玻璃键合(SOG)方法制作.将数值模拟结果与实验结果比较发现,无论是流动速度还是流动前沿的形态,两者均呈现出较高的吻合度.这表明:针对下填充流动的二维化数值分析方法兼具高效性和准确性,具有较高的应用价值.     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects