真空环境下的共晶焊接

共晶焊接是微电子组装中一种重要的焊接工艺。文章简要介绍了共晶焊接的工作原理以及共晶焊料如何选用和常用共晶焊料的性能特性。然后比较了几种共晶焊接设备的优缺点,得出用真空可控气氛共晶炉在真空环境下完成共晶焊接能有效防止共晶焊接过程中氧化物的产生,大大降低空洞率,从而提高焊接质量。它同样适用于多芯片组件的一次共晶。对真空环境下影响共晶焊接质量的真空度、保护性气氛、焊接过程中的温度曲线、焊接时的压力等条件做了探讨,得出了几种最优的工艺方案,能适用于大部分的共晶焊接工艺。     

微波GaAs功率芯片的低空洞率真空焊接技术研究

文章选用80Au20Sn焊料对微波GaAs功率芯片的焊接技术进行了较为系统深入的研究,通过对共晶焊接设备与真空烧结设备分别对焊接时气体保护、焊片大小、真空工艺过程的施加和夹具设计等因素进行了试验分析。结果表明,以上参数对微波GaAs功率芯片焊接均有显著的影响,在保护气体流量为1.5L·min^-1的氮气保护下,通过施加适当的夹具静压力和金锡焊料熔化时的抽真空应用,AuSn焊料能够充分和快速润湿,实现较高的焊接质量。X射线检测结果表明,微波GaAs功率芯片焊接具有较低的空洞率,焊透率高达90％以上,焊接过程主要通过夹具装配完成,人为影响因素少,成品率高。     

微波功率芯片真空焊接工艺研究

使用真空焊接技术焊接微波功率芯片可以降低焊接空洞率和提高焊接可靠性。微波功率芯片由于其表面存在空气桥,增加了焊接夹具的设计与制作难度,同时也增加了生产过程中的操作难度,因而研究微波芯片的真空焊接很有意义。阐述了采用金锡共晶焊料真空焊接微波功率芯片的相关问题,重点介绍了真空焊接原理和真空焊接工艺设计,根据实验结果总结和分析了影响焊接质量的因素。     

共晶焊料焊接的孔隙率研究

大功率或高功率密度的高可靠集成电路等通常采用合金焊料焊接芯片,以降低封装热阻和提高芯片焊接的可靠性。合金焊料焊接方式主要有真空烧结、保护气氛下静压烧结、共晶摩擦焊等。不同焊接工艺有其不同的适应性和焊接可靠性。文章以高可靠封装常用金基焊料的共晶焊接为例,探讨在相同封装结构、不同共晶焊接工艺下焊接层孔隙率,以及相同工艺设备、工艺条件下随芯片尺寸增大孔隙率的变化趋势。研究结果表明:金-硅共晶摩擦焊工艺的孔隙率低于金-锡真空烧结工艺和金-锡保护气氛静压烧结;同一焊接工艺,随着芯片尺寸变大,其孔隙率变化不显著,但单个空洞的尺寸有明显增大趋势。     

真空共晶设备的改进对共晶焊接质量的影响

共晶焊接质量对芯片的可靠性及寿命影响很大。在这方面,通过改进后的真空共晶设备比改进前更具有优势。分析了真空环境对共晶焊接的影响,在原有设备增加了分子泵的情况下,实现无空洞焊接。对甲酸气体保护下的In焊料焊接进行了分析,并结合实际经验给出合理的工艺曲线,证实了在真空室加入甲酸气体的保护下,可以把In焊料表面的氧化层去除,使焊料在浸润性方面具有明显的优势。     

真空共晶焊接金属电极片变色问题改善工艺研究

多芯片组装共晶焊接技术是在芯片的端部和金属电极片之间添加焊料,在合适的温度、时间、真空度以及气氛下实现两表面的共晶物熔合,具有低空洞率、焊接强度高等优点.封闭的炉腔内焊料中的挥发物和氧气会造成金属电极片变色,且无法利用清洗剂去除.通过对炉腔内气氛、真空度等工艺进行试验研究,分析不同的真空度与金属电极片变色之间的关系.试...     

无空洞真空共晶技术及应用

在采用功率芯片集成产品时,往往要求热阻小,可靠性高.在这方面,真空共晶技术与传统的芯片贴装方法如环氧粘结或者手动氮气保护共晶技术相比更具优势.分析了真空环境对共晶焊接的影响,同时对影响真空共晶焊接的工艺因素进行了剖析,通过这些因素的控制,可以得到无空洞的焊接.同时给出了真空共晶技术可能的应用.     

金锡合金自动共晶焊接工艺参数优化研究

为了更好地控制共晶焊接空洞率和剪切力,提出了一种采用正交试验法优化自动共晶焊接参数的方法。对焊接温度、焊接时间、焊接压力三个关键参数采用正交法进行三因子两水平极差分析,得到了影响芯片金锡共晶焊接质量的主次因子及共晶焊接参数的最优组合。试验结果证明,使用优化的工艺参数,芯片焊接质量得到明显提升,共晶焊接区空洞率均值及芯片剪切力Cpk值均完全满足GJB548B的要求。     

薄膜基板芯片共晶焊技术研究

共晶焊是微电子组装技术中的一种重要焊接工艺,在混合集成电路中得到了越来越多的应用。文章简要介绍了共晶焊接的原理,分析了影响薄膜基板与芯片共晶焊的各种因素,并且选用Ti/Ni/Au膜系和AuSn焊料,利用工装夹具在真空环境下通入氮、氢保护气体的方法进行薄膜基板芯片共晶焊技术的研究。试验证明:焊接基板金属化Au层厚度1.5μm,焊接压力为2kPa,焊接温度330℃,时间30s可有效地使空洞面积控制在10%以下。并在150℃高温贮存以及-65℃~150℃温度循环后对共晶焊接样品的剪切强度和接触电阻进行了试验。在可靠性试验后,样品的剪切强度满足GJB548B-2005的要求,接触电阻变化率小于5%。     

芯片共晶模块高钎透率真空回流焊接工艺

芯片共晶模块是微波组件的重要组成部分，芯片共晶模块到壳体封装质量直接影响微波组件的电学性能和可靠性。采用真空回流焊接技术对芯片共晶模块进行低温焊接，通过优化压块材质、温度曲线和真空制程参数等方式，实现芯片共晶模块焊接钎透率达90%以上、单个空洞率低于5%的标准要求。     

Effect of voids on thermo-mechanical reliability of chip resistor solder joints: Experiment,modelling and simulation

With the introduction of lead-free solder alloys, the effect of voids on solder joint reliability has rapidly gained importance. In this study, a first analysis of X-rayed CR0805 solder joints shows a significant reduction in void content, from 20% down to 2.5%, after vacuum soldering. The statistical analysis of the void distribution demonstrates that the vacuum option reduces number of voids and median diameter of voids in comparison to the convection soldering process. A subsequent accelerated thermal cycling test of these analysed test vehicles, according to JESD22-A104D, indicates the tendency of a higher characteristic life time for higher void content. In contrast to these findings, the 1% to failure criterion reveals a higher reliability for lower voiding. During the finite element method (FEM) modelling part of this study, two modelling approaches of void implementation into solder joint geometry are investigated: modelling with a constant volume of the standoff for different void contents, and a modelling approach with a random combination of void content and volume of standoff. The modelling approach with the random combination reveals that voids can reduce the lifetime in the “worst case” parameter combination. In particular, the 1% time to failure rate indicates a quantitative correlation with the experimental results. Furthermore, the FEM results suggest a higher impact on reliability for a single void in comparison to a distribution of multiple voids with similar void content. Finally, the FEM study shows a high sensitivity of predicted life time with respect to the standoff height. Based on this finding, the CR0805 solder joint geometry is examined using optical inspection and cross-section polishes with the outcome that the better wetting behaviour during vacuum soldering causes a reduction of the solder alloy volume and consequently further decreases the standoff height.     

The effect of soldering process variables on the microstructure and mechanical properties of eutectic Sn-Ag/Cu solder joints

Fundamental understanding of the relationship among process, microstructure, and mechanical properties is essential to solder alloy design, soldering process development, and joint reliability prediction and optimization. This research focused on the process-structure-property relationship in eutectic Sn-Ag/Cu solder joints. As a Pb-free alternative, eutectic Sn-Ag solder offers enhanced mechanical properties, good wettability on Cu and Cu alloys, and the potential for a broader range of application compared to eutectic Sn-Pb solder. The relationship between soldering process parameters (soldering temperature, reflow time, and cooling rate) and joint microstructure was studied systemati-cally. Microhardness, tensile shear strength, and shear creep strength were measured and the relationship between the joint microstructures and mechani-cal properties was determined. Based on these results, low soldering tempera-tures, fast cooling rates, and short reflow times are suggested for producing joints with the best shear strength, ductility, and creep resistance.     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

波峰焊焊接空洞问题的分析与解决方法

无铅波峰焊接工艺是常见组装焊接工艺之一,其中焊接空洞是较严重的问题。焊接空洞的存在是电子学产品的潜在隐患,影响产线补板效率,增加生产成本。以实际生产过程中混装电路板过波峰焊时遇到的通孔焊接空洞现象进行分析,主要从印制板制程工艺与波峰焊工艺参数这两方面提出解决方案。     

贴片电阻焊点内部空洞缺陷自适应检测

贴片电阻在回流焊过程中,受工艺影响,焊点内部或多或少会存在空洞缺陷,空洞占比率过高会严重降低器件的可靠性。该文融合局部预拟合(LPF)活动轮廓模型和自适应圆形卷积核,提出一种贴片电阻焊点内部空洞缺陷自适应检测方法。首先,根据贴片电阻图像具有明暗两个明显区域的特点,通过求解区域平均灰度差异最大的优化问题将其自适应地分为较暗和较亮两个区域。然后,针对较暗区域中空洞与背景之间对比度低、空洞分布较稀疏、面积偏大等特点,采用局部预拟合活动轮廓模型进行空洞检测;针对较亮区域中空洞与背景之间差异明显、空洞分布密集、面积偏小等特点,提出一种自适应圆形卷积核检测空洞。最后,采用形状因子和平均灰度策略剔除误检测,实现贴片电阻焊点内部空洞精细检测。实验结果表明,该文算法相较于其他检测算法性能有明显的提升,平均Dice系数高达0.8846。