HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm², and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he was with the NEC Information Technology Research Laboratories, Kawasaki, Japan, working on efficient implementations of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Sören Moch received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1997.Since then he has been Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of processor architectures for image, video and multimedia signal processing applications.Lars Friebe studied electrical engineering at the Universities Ulm and Hannover, Germany. In 1999, he worked at the NEC System ULSI Research Laboratory in Kanagawa, Japan. He received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1999.Since then he has been a Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of parallel programmable VLSI architectures for real-time image processing.Mark B. Kulaczewski started his studies in electrical engineering at the University of Hannover, Germany. In 1994, he transferred to Purdue University, West Lafayette, USA, and received the M.S. degree in electrical engineering in 1996.Since 1997 he has been a Research Assistant at the Laboratory for Information Technology and the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable real-time architectures for video coding and image segmentation, and instruction-set extensions for cryptographic applications.Sebastian Flügel was born in Crivitz, Germany, in 1975. He received his Dipl.-Ing. degree from the Department of Electrical Engineering of the University of Rostock in 2001.Since then he has been a Ph.D. candidate at the Institute of Microelectronic Systems at the University of Hannover. He works in the field of architectures and systems for video processing systems. His focus is on algorithms for video encoding and the development of optimized hardware architectures.Heiko Klußmann received the Dipl.-Ing. degree in computer engineering from the University of Hannover, Germany, in 2002.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests are in the area of programmable architectures for real-time video signal processing.Andreas Dehnhardt was born in Frankfurt am Main, Germany, in 1976. He received his Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 2002.Since then, he has been a Research Assistant with the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable architectures for multimedia applications and implementation of real-time MPEG-4 encoding schemes.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1980 and in Summer 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL research center, Stuttgart. Since 1987 he is Professor in the Department of Electrical Engineering, since 2002 in the Department of Computer Science at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002. His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

“数字信号处理”测角与测距实验设计

“数字信号处理”课程的理论性强、公式繁琐,课程实验设计有助于提升学生对抽象理论的理解。针对目前课程实验与实际工程问题联系性不强,本文设计了基于Matlab仿真平台的声源方位角估计与探地雷达地表探测实验。实验内容涵盖信号卷积与相关、频谱分析以及快速傅里叶变换等重要基础知识。实验效果表明学生加深了对基本理论知识的理解,提高了理论联系实际和解决复杂工程问题的能力。     

Architecture Concepts for Multimedia Signal Processing

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.     

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation. The methodology distinguishes between applications and architectures, and uses a trace-driven simulation technique for co-simulation of application models and architecture models. As a consequence, architecture models need not be functionally complete to be used for performance analysis while data dependent behavior is still handled correctly. We have used the methodology for the exploration of architectures and mappings of an MPEG-2 video decoder application.     

Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations

MPEG-4 is a new multimedia standard combining interactivity, object-based natural and synthetic digital video, audio and computer-graphics. For the implementation of the video part of the MPEG-4 standard a high degree of flexibility is required, where the motion estimation requires the highest part of the computational power. Therefore, in this paper fast algorithms for MPEG-4 motion estimation are evaluated in terms of visual quality and computational power requirements for processor based implementations. Due to the object-based nature of MPEG-4 also new VLSI architectures for MPEG-4 motion estimation are required. Therefore known motion estimation architectures are evaluated on their capability of being modified for MPEG-4 support. Based on this evaluation a new dedicated, but flexible MPEG-4 motion estimation architecture targeted for low-power handheld applications is presented, which resulted to be advantageous to processor based implementations by magnitudes of order.     

一种基于数字信号处理器的媒体处理器结构及设计

设计了一种针对图像、音频、视频等多媒体数据的处理新型结构的媒体处理器。该媒体处理器由一个通用数字信号处理器及多媒体协处理器构成,其指令集包含了通用的数字信号处理指令及扩展的多媒体处理指令。多媒体协处理器中包含了多个专用于多媒体处理的功能模块,可以加速多媒体处理的进行。该媒体处理器具有强大的多媒体处理能力,可实现对JPEG压缩图像、MP3音频流或MPEG2的MP@ML级别的压缩视频流的实时解码。     

TMS320C5402DSK板在数字信号处理实验中的应用

通过对数字信号处理课程的改革，增加了DSP系统的设计和开发的课程，拓宽高校电子工程类专业学生在DSP方面的知识，进一步培养他们的动手能力和创新能力。该课程实验中需要使用到初学者开发套件——美国TI公司的TMS320C5402DSK。本文将重点介绍该DSK板的硬件体系，并且简要介绍了与该硬件体系相对应的CCS2.0限制版集成开发环境，并进一步讨论了在此套件基础上所开设的一系列DSP实验内容。     

基于ADSP-BF561车载多媒体系统

给出一套新的车载多媒体系统设计方案,该系统是基于美国模拟器件公司(AnalogDeviceInc.,ADI)最新发布的ADSP-BF561嵌入式多媒体处理器设计出的支持嵌入式音视频应用,GPS,GPRS,HFCK,网口,USB,CAN总线,I2C控制和海量存储等功能,是功能强大的多媒体系统,尤其适用于车载环境,亦可作为个人数字助理应用。     

数字信号处理课程教学改革的探索与体会

针对"数字信号处理"课程实用性强、理论内容丰富但概念抽象难懂等特点,结合我校课程教学实际情况,从教学和实验两个环节进行了改革.在教学环节上精选教学内容、优化教学方法、丰富教学手段、突出概念的物理意义及应用、指导学生有针对性的做题;在实验过程改革考核机制,增加综合设计性实验,注重培养学生理论联系实际、独立分析解决问题的能力.实践表明教学改革取得了较好的效果.     

中频数字信号处理的DSP实现

介绍了软件无线电中频数字信号的处理方法及原理,并着重介绍了采用数字信号处理器(DSP)直接对中频数字信号进行数字下变频、基带和数字上变频的处理,从而使中频数字信号的处理更加灵活和方便。     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

C55x系列DSP在基带信号处理中的应用与实现

本文分析了TI公司的C55x系列DSP的特点,详细介绍了基于C55x系列DSP实现基带信号处理中的crc校验,卷积编码,维特比译码,交织/去交织等信道中的编解码。     

稳健估计的自适应信号处理方法

本文把应用数学学科研究的热门方法之一“稳健估计”应用于自适应信号处理系统中，理论分析和计算机模拟结果都证明ＲＥ方法在实际应用中，基本保持了最小二乘估计的优点。     

Reconfigurable Coprocessor for Multimedia Application Domain

A new reconfigurable architectural template is presented. Such a template is composed of coarse-grained and fine-grained reconfigurable datapath and control to obtain performances at custom designed chip level. To show the adaptability/performance of such architectural template, the architecture has been customized (i.e. datapath and control features of the template have been properly sized) for multimedia application domain. To evaluate complexity and maximum clock frequency of the proposed architecture, it has been synthesized using Synopsys Design Compiler on a standard-cell 0.18 μ m technology. Estimated number of transistors is 335 K, while maximum allowable frequency is 460 MHz. Performances have been evaluated comparing the number of clock cycles and the processing time required to process application domain dominant kernels with commercial devices: we obtained up to 95% reduction with respect to ARM and up to 94% reduction with respect to TMS320C5510 in terms of clock cycles. Salvatore M. Carta (1997 Electronic Eng. Master. 2002 Electronics and Computer Science PhD) joined the Department of Electrical and Electronics Engineering of the University of Cagliari, Italy in 1998 as PhD student. From 2005 he has been assistant professor in Department of Mathematics and Computer Science of the University of Cagliari. His research interests focus mainly on architectures, software and tools for embedded and portable computing, with particular emphasis on: languages, architectures and compilers for reconfigurable and parallel computing; Networks-on-chip; Operating systems for multiprocessor-systems-on-chip; low power real-time scheduling algorithms. Danilo Pani (2002 Electronic Eng. Master, 2006 Electronics and Computer Science PhD) joined the Department of Electrical and Electronics engineering of the University of Cagliari, Italy in 2002 as Electronics and Computer Science PhD student. His primary research interests are in the area of Digital Signal Processing architectures and systems, Biomedical Engineering, Reconfigurable Systems and Cooperative VLSI architectures for distributed computing. Luigi Raffo (1989 Master, 1994 Electronics and Computer Science PhD) joined Department of Electrical and Electronics Engineering of the University of Cagliari, Italy in 1994 as assistant professor. From 1998 he has been professor of Digital System Design, Integrated Systems Architectures and Microelectronics at the same Department. His research activity is mainly in the design of low-power analog and digital architectures/chips. He has been project manager of many local and international projects. He is author of more than 50 international papers in the field.     

“数字信号处理”课程的Matlab教学研究

＂数字信号处理＂是一门理论理论性和实践性都很强的课程,针对教学过程中出现的学生对知识点理解困难、学习枯燥无味、教学效果差等问题,本文将Matlab软件引入课堂教学过程中,给出了利用DFT做连续信号频谱分析的实例,将抽象的概念、枯燥的公式、复杂的物理现象用图形化演示直观地表示出来,使学生直观地领会、深入地理解数字信号处理的理论知识和分析设计方法,提高了教学质量。     

一种基于DSP的并行信号处理系统的设计

讨论了一种并行信号处理系统，该系统采用高性能的并行DSP芯片作为处理单元，构成了分布式的并行结构，具有很强的可扩充性和灵活性。算法软件和数据传输软件的标准模块用汇编语言完成，以达到高效地实时处理；主程序用高级语言设计，可以方便地调用各标准软件模块，整个程序具备易修改、易维护的特点。     

Matlab在"数字信号处理"课程中的应用

本文利用Matlab软件,以复合信号分离为例,对数字信号处理课程中的谱分析、数字滤波器设计和信号滤波这三个过程进行了仿真实现,给出了仿真结果。将Matlab应用于数字信号处理课程教学,可以帮助学生理解与掌握课程中的基本概念和基本分析方法,在激发学生学习兴趣同时,有效地提高了课堂教学质量。     

多体制雷达视频信号模拟器设计

分析雷达视频信号模拟器的通用结构,并根据多体制尖信号模拟器的要求,设计出基于模块化的结构灵活,参数可变的信号模拟器。为解决模拟器所需海量存储器与物理实现之间的矛盾,提出一种随机抽取法,利用有限杂波,噪声模拟海量伪独立分布杂波、噪声,收到了较好的效果。     

时空二维信号的非自适应准最佳处理＊

本文提出了一种时空二维信号的非自适应准最佳处理新方法。用时间和空间对消器分别对消掉与目标同方向的主杂波和与目标同多普勒频率的副瓣杂波,然后用时间和空间滤波器滤除其余杂波,与其它方法相比,该方法运算量最小,能实现实时处理,且性能接近最佳。     

“数字信号处理”课程教学方式改革

本文介绍如何将"数字信号处理"课程教学看作一个有机体,系统地安排其概念、用途、理论、方法、效率和实践等教学内容。教师应尽量顺应社会的需求和学生的特点,循序渐进,并按教学内容的进展配置相应的实例和趣味实验,提高学生的能动性。学生在学习多门课程的情况下,提高了本门课程的学习效率,学到"数字信号处理"的更多知识和培养创新的意识。