2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.     

2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.     

An Ultra-Compact CMOS Variable Phase Shifter for 2.4-GHz ISM Applications

An ultra-compact monolithic microwave integrated circuit active variable phase shifter is proposed and implemented using CMOS technology. It is a reflective-type phase shifter consisting of a compact three-transistor active circulator and a second-order LC network. The use of an active inductor in the second-order LC network makes this phase shifter all active and ultra compact with a size of only 0.357 including bonding pads. The phase shifter was designed and demonstrated at 2.4 GHz and has a linear and continuously tunable range of 120 across the 2.4-GHz industrial-scientific-medical band.     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications

A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI/sub pp/ at 10 GHz and a phase noise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.     

A low-power 2/5.8-GHz dual-wide-band CMOS LC-VCO with switched-inductor technique

A fully integrated dual-band LC voltage control oscillator, designed in a 0.18-µm CMOS technology for 5.8-GHz/2.0-GHz wireless communication applications, is described. The frequency band switching is accomplished with switched-inductor technique. The dual-band oscillator can be operated in 5.38–6.23?GHz and 1.78–2.07?GHz with 15% frequency tuning range. Two different inductors are used for the frequency band switching. Frequency tuning is implemented by varying the capacitance of a MOS varactor. The measured phase noise is ?109?dBc/Hz @ 1?MHz and ?112?dBc/Hz @ 1?MHz for frequency at 5.8?GHz and 2?GHz, respectively. This oscillator is fabricated in UMC's 0.18-µm one-poly-six-metal 1.8?V process. The power dissipation of this dual-band VCO is 11.7 and 9.3?mW for oscillation frequency of 2?GHz and 5.8?GHz, respectively.     

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.     

变压器反馈的超低功耗低相位噪声CMOSLC-VCO设计

设计了一种全集成交叉耦合变压器反馈的LC压控振荡器(LC-VCO),该VCO在电源电压低于阈值电压的情况下实现了超低功率消耗和低相位噪声.该超低功耗的VCO采用SMIC 0.18μm数模混合RF 1P6M CMOS工艺进行了流片验证.测试结果表明:电路在0.4V电源供电和工作频率为2.433GHz时,相位噪声为-125.3dBc/Hz(频偏1MHz),核心直流功耗仅为720μW.芯片的工作频率为2.28～2.48GHz,调谐范围为200MHz(8.7%),电路的优值为-193.7dB,信号的输出功率约为1dBm.该VCO完全可以满足IEEE 802.11b接收机的应用要求.     

A 1-V 5-GHz CMOS Multiple Magnetic Feedback Receiver Front-End

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-mum CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of .     

运用共模响应整形技术实现恒跨导全摆幅运放

本文提出了一种运用“共模响应整形技术”实现的恒跨导全摆幅运放。该运放在全摆幅的动态工作范围内，输入级跨导基本保持不变。CMOS工艺参数的变化对跨导变化率的影响很小。输出级采用AB类结构，实现了全摆幅输出。     

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-μm CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

An Ultra-Compact Hairpin Band Pass Filter With Additional Zero Points

A novel quasi-hairpin filter is presented in this letter. The filter shows ultra-compact size, steep selectivity, and deep stopband rejection with additional transmission zero points. The fourth-order filter operating at 1.69GHz with a fractional bandwidth of 10% occupies the active area of 5.5mmtimes6.2mm (0.031lambda₀times0.035lambda₀)     

A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-mum CMOS process ( V and V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated with the structure is suppressed by two common-mode stabilization loops. The amplifier driving 100-pF loads achieves a 4.3-MHz gain-bandwidth product. The settling time of a 1- input step signal is 1.1s. The amplifier consumes 249 muW and occupies 0.06-mm silicon area.     

一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器,集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时,在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时,不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.     

A 6-GHz capacitively-coupled Colpitts CMOS quadrature voltage controlled oscillator

In this work a new low-noise low-power Colpitts quadrature voltage controlled oscillator (QVCO) made by coupling two identical current-switching differential Colpitts voltage controlled oscillators (VCO) is proposed; coupling of the VCOs is done using some capacitors in an “in-phase anti-phase” scheme. In this coupling configuration first harmonics (as well as higher harmonics) from each VCO are injected to the other VCO, as opposed to coupling schemes in which only even harmonics are injected. An analysis of the linearized circuit which confirms 90° phase difference between output signals of the proposed circuit is presented. Since no extra noise sources or power consumption are introduced to the core VCOs, the proposed QVCO achieves low phase noise performance and low power consumption. The proposed circuit is designed and simulated in a commercial 0.18 μm CMOS technology. The simulated phase noise of the proposed QVCO at 3 MHz offset frequency is ?138.3 dBc/Hz, at 6 GHz. The circuit dissipates 8.16 mW from a 1.8 V supply and its frequency can be tuned from 5.6 to 6.3 GHz.     

An Ultra-Compact Planar Bandpass Filter With Open-Ground Spiral for Wireless Application

A common via filter is investigated and designed by using a proposed scalable lumped circuit model. The model-based result of the filter agrees well with that of the measurement. An ultra-compact open-ground spiral filter is proposed based on the common via filter. The open-ground spiral resonators are used to design second-order and fourth-order bandpass filters. The filter layouts, which affect filter performance in both passband and stopband, are investigated. The advantages of the open-ground spiral filter include not only its ultra-compact size (only ) but also its additional transmission zero points and controllable stopband.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.     

A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-psjitter in 0.18-μm standard digital CMOS copper technology

In this paper, we present a fully integrated frequency synthesizer, using an LC voltage-controlled oscillator (LC-VCO) as the core oscillator. The synthesizer is designed to provide various output clock signals for a transceiver chip. Sampling clocks for on-chip analog-to-digital and digital-to-analog conversion modules are also generated, where low jitter is required. The synthesizer also includes an additional digital phase-locked loop and programmable fractional dividers. We present the general concept, special issues related to low jitter, and test chip results. The synthesizer achieves 3-ps rms long-term jitter on a 200-MHz output with 20-mW power and an area of 0.7 mm²