An Ultra-Compact CMOS Variable Phase Shifter for 2.4-GHz ISM Applications

An ultra-compact monolithic microwave integrated circuit active variable phase shifter is proposed and implemented using CMOS technology. It is a reflective-type phase shifter consisting of a compact three-transistor active circulator and a second-order LC network. The use of an active inductor in the second-order LC network makes this phase shifter all active and ultra compact with a size of only 0.357 including bonding pads. The phase shifter was designed and demonstrated at 2.4 GHz and has a linear and continuously tunable range of 120 across the 2.4-GHz industrial-scientific-medical band.     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications

A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI/sub pp/ at 10 GHz and a phase noise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.     

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.     

A 1-V 5-GHz CMOS Multiple Magnetic Feedback Receiver Front-End

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-mum CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of .     

运用共模响应整形技术实现恒跨导全摆幅运放

本文提出了一种运用“共模响应整形技术”实现的恒跨导全摆幅运放。该运放在全摆幅的动态工作范围内，输入级跨导基本保持不变。CMOS工艺参数的变化对跨导变化率的影响很小。输出级采用AB类结构，实现了全摆幅输出。     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-μm CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications     

An Ultra-Compact Hairpin Band Pass Filter With Additional Zero Points

A novel quasi-hairpin filter is presented in this letter. The filter shows ultra-compact size, steep selectivity, and deep stopband rejection with additional transmission zero points. The fourth-order filter operating at 1.69GHz with a fractional bandwidth of 10% occupies the active area of 5.5mmtimes6.2mm (0.031lambda₀times0.035lambda₀)     

A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-mum CMOS process ( V and V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated with the structure is suppressed by two common-mode stabilization loops. The amplifier driving 100-pF loads achieves a 4.3-MHz gain-bandwidth product. The settling time of a 1- input step signal is 1.1s. The amplifier consumes 249 muW and occupies 0.06-mm silicon area.     

A 6-GHz capacitively-coupled Colpitts CMOS quadrature voltage controlled oscillator

In this work a new low-noise low-power Colpitts quadrature voltage controlled oscillator (QVCO) made by coupling two identical current-switching differential Colpitts voltage controlled oscillators (VCO) is proposed; coupling of the VCOs is done using some capacitors in an “in-phase anti-phase” scheme. In this coupling configuration first harmonics (as well as higher harmonics) from each VCO are injected to the other VCO, as opposed to coupling schemes in which only even harmonics are injected. An analysis of the linearized circuit which confirms 90° phase difference between output signals of the proposed circuit is presented. Since no extra noise sources or power consumption are introduced to the core VCOs, the proposed QVCO achieves low phase noise performance and low power consumption. The proposed circuit is designed and simulated in a commercial 0.18 μm CMOS technology. The simulated phase noise of the proposed QVCO at 3 MHz offset frequency is ?138.3 dBc/Hz, at 6 GHz. The circuit dissipates 8.16 mW from a 1.8 V supply and its frequency can be tuned from 5.6 to 6.3 GHz.     

An Ultra-Compact Planar Bandpass Filter With Open-Ground Spiral for Wireless Application

A common via filter is investigated and designed by using a proposed scalable lumped circuit model. The model-based result of the filter agrees well with that of the measurement. An ultra-compact open-ground spiral filter is proposed based on the common via filter. The open-ground spiral resonators are used to design second-order and fourth-order bandpass filters. The filter layouts, which affect filter performance in both passband and stopband, are investigated. The advantages of the open-ground spiral filter include not only its ultra-compact size (only ) but also its additional transmission zero points and controllable stopband.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.     

A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-psjitter in 0.18-μm standard digital CMOS copper technology

In this paper, we present a fully integrated frequency synthesizer, using an LC voltage-controlled oscillator (LC-VCO) as the core oscillator. The synthesizer is designed to provide various output clock signals for a transceiver chip. Sampling clocks for on-chip analog-to-digital and digital-to-analog conversion modules are also generated, where low jitter is required. The synthesizer also includes an additional digital phase-locked loop and programmable fractional dividers. We present the general concept, special issues related to low jitter, and test chip results. The synthesizer achieves 3-ps rms long-term jitter on a 200-MHz output with 20-mW power and an area of 0.7 mm²     

A 12-GHz Fully Integrated Cascode CMOS LC VCO With Q-Enhancement Circuit

A fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise. The symmetrical cascode architecture is implemented with negative conductance circuit for improving phase noise performance in 0.18 mum CMOS technology. The measured phase noise is -110.8 dBc/Hz at the offset frequency of 1 MHz. The tuning range of 630 MHz is achieved with the control voltage from 0.6 to 1.4 V. The VCO draws 4.5 mA in a differential core circuit from 1.8 V supply.     

5-GHz Low Phase-Noise CMOS VCO Integrated With a Micromachined Switchable Differential Inductor

A 5-GHz CMOS voltage-controlled oscillator (VCO) integrated with a micromachined switchable differential inductor is reported in a 0.18 mum radio frequency-CMOS-based microelectromechanical system technology. The power consumption of the core is about 8 mW at the supply voltage of 1.8 V. A total tuning range of 470 MHz (from 5.13 GHz to 5.60 GHz) is achieved as the tuning voltage ranging from 0 V to 1.8 V. In the practical tuning range, the measured phase noise performances at 1 MHz offset are less than -125 dBc/Hz and -126 dBc/Hz when the inductor switch is turned on and off, respectively. The figure-of-merit is better than -190 dB. When compared with a contrast VCO circuit that utilizes a standard switchable differential inductor, this oscillator reaches a phase noise improvement of around 3 dB as the switch is turned on. Around 1-dB on-off phase noise difference can be achievable.     

A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification

In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced     

High-Voltage-Gain CMOS LNA For 6–8.5-GHz UWB Receivers

The design of a fully integrated CMOS low noise amplifiers (LNA) for ultra-wide-band (UWB) integrated receivers is presented. An original LC input matching cell architecture enables fractional bandwidths of about 25%, with practical values, that match the new ECC 6–8.5-GHz UWB frequency band. An associated design method which allows low noise figure and high voltage gain is also presented. Measurements results on an LNA prototype fabricated in a 0.13- $mu$m standard CMOS process show average voltage gain and noise figure of 29.5 and 4.5 dB, respectively.      

A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-/spl mu/m one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm/sup 2/.     

A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO

A fully symmetrical integrated quadrature LC oscillator with a wide tuning range of 1.2GHz is presented. The quadrature voltage-controlled oscillator (QVCO) is implemented using a symmetrical coupling method which has been used to produce the large tuning range with a low control voltage and to achieve good phase noise performance in 0.18/spl mu/m complementary metal oxide semiconductor technology. The measured phase noise at 1MHz offset from the center frequency (5.5GHz) is -115 dBc/Hz. The QVCO draws 3.2mA from a 1.8V supply. The equivalent phase error between I and Q signal was at most 0.5/spl deg/.