Industrial application of heterostructure device simulation

We give an overview of the state-of-the-art of heterostructure RF-device simulation for industrial application based on III-V compound semiconductors. The work includes a detailed comparison of device simulators and current transport models to be used, and addresses critical modeling issues. Results from two-dimensional hydrodynamic simulations of heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs) with MINIMOS-NT are presented in good agreement with measured data. The simulation examples are chosen to demonstrate technologically important issues which can be addressed and solved by device simulation.     

GaN nanowires on diamond

The current research of GaN nanowires on diamond substrates is reviewed and extended by recent results. Both the self-assembled and the selective area growth mechanisms using plasma-assisted molecular beam epitaxy are summarized. Structural and optical properties of as-grown nanowires as well as doping-related issues are discussed and compared to nanowires on silicon substrate. The electronic characteristics of p-diamond/n-GaN nanowire heterojunctions are addressed theoretically by band structure simulations and experimentally by transport measurements. Finally, electroluminescence of a fabricated prototype nanoLED device is demonstrated.     

Reprint of: GaN nanowires on diamond

The current research of GaN nanowires on diamond substrates is reviewed and extended by recent results. Both the self-assembled and the selective area growth mechanisms using plasma-assisted molecular beam epitaxy are summarized. Structural and optical properties of as-grown nanowires as well as doping-related issues are discussed and compared to nanowires on silicon substrate. The electronic characteristics of p-diamond/n-GaN nanowire heterojunctions are addressed theoretically by band structure simulations and experimentally by transport measurements. Finally, electroluminescence of a fabricated prototype nanoLED device is demonstrated.     

Design of 50-nm vertical MOSFET incorporating a dielectric pocket

A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.     

Two‐terminal metal‐inter‐connected multijunction III–V solar cells

A novel bonding approach with an interface consisting of a metal and dielectric is developed, and a “pillar‐array” metal topology is proposed for minimal optical and electrical loss at the interface. This enables a fully lattice‐matched two‐terminal, four‐junction device that consists of an inverted top two‐junction (2J) cell with 1.85 eV GaInP/1.42 eV GaAs, and an upright lower 2J cell with ~1 eV GaInAsP/0.74 eV GaInAs aimed for concentrator applications. The fabrication process and simulation of the metal topology are discussed along with the results of GaAs/GaInAs 2J and (GaInP + GaAs)/GaInAs three‐junction bonded cells. Bonding‐related issues are also addressed along with optical coupling across the bonding interface. Copyright © 2014 John Wiley & Sons, Ltd.     

A new device design methodology for manufacturability

As future technology generations for integrated circuits continue to “shrink”, TCAD tools must be made more central to manufacturing issues; thus, yield optimization and design for manufacturing (DFM) should be addressed integrally with performance and reliability when using TCAD during the initial product design. This paper defines the goals for DFM in TCAD simulations and outlines a formal procedure for achieving an optimized result (ODFM). New design of experiments (DOE), weighted least squares modeling and multiple-objective mean-variance optimization methods are developed as significant parts of the new ODFM procedure. Examples of designing a 0.18-μm MOSFET device are given to show the impact of device design procedures on device performance distributions and sensitivity variance profiles     

Improving mobile network performance with two queueing buffer allocations of priority-based queueing scheme

As current mobile core network systems are expected to evolve into all-IP networks, packet switching will be a prerequisite for all mobile applications. Next-generation mobile networks, as envisioned by ITU-T, are packet-based networks capable of providing consistent and ubiquitous service to end users, independent of the network, access technology, and device used. This study discusses the differentiated packet forwarding performance of four major types of mobile network traffic under the proposed mobile network priority-based queueing (MPQ) scheme with two queueing buffer allocations, namely dynamic queueing buffer (DQB) allocation and overflow queueing buffer (OQB) allocation. As different queueing buffer allocations are adopted to store arriving packets in DQB and OQB, the MPQ scheme shows different packet forwarding performance under these two methods. In this study, we use ns2 (Network Simulator version 2) as the simulation platform to simulate several scenarios. The simulation results show that the MPQ scheme is able to support differentiated packet forwarding behavior for mobile traffic with both DQB and OQB allocations in a mobile core network. Some issues were identified in the MPQ scheme with both DQB and OQB allocation, which will need to be addressed.     

Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour

High-voltage power MOSFETs have been widely used in switching mode power supply circuits as output drivers for industrial and automotive electronic control systems. However, as the device size is reduced, the energy handling capability is becoming a very important issue to be addressed together with the trade-off between the series on-resistance R_ON and breakdown voltage V_BR. Unclamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the “ruggedness”, which characterizes the device capability to handle high avalanche currents during the applied stress. In this paper we present an experimental method which modifies the standard UIS test and allows extraction of the maximum device temperature after the applied standard stress pulse vanishes. Corresponding analysis and non-destructive prediction of the ruggedness of power DMOSFETs devices supported by advanced 2-D mixed mode electro-thermal device and circuit simulation under UIS conditions using calibrated physical models is provided also. The results of numerical simulation are in a very good correlation with experimental characteristics and contribute to their physical interpretation by identification of the mechanism of heat generation and heat source location and continuous temperature extraction.     

AUTOREC: an automated error recovery system for network management

The system, which was developed and is being used by AT&T to do error detection and recovery on a packet switching network, is described. Some of the major design issues that were addressed in developing AUTOREC are examined. These include system scope, hardware considerations, language selection, the multiple vendor problem, device recovery capability, and expansion. AUTOREC's modular architecture is described, and how an operator would interface with the system is explained. Some of the benefits that have resulted from the project and some of the lessons learned are discussed     

SOI for digital CMOS VLSI: design considerations and advances

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues     

Modeling and simulation of single-event effect in CMOS circuit

This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ionization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.     

Noise optimisation for the design of a reliable high speed X-ray readout integrated circuit

On the basis of the design of an X-ray readout integrated circuit, we present in this paper the noise analysis which has to be performed in order to implement a reliable system. In this context, we exploit the various noise sources originating both at the device and at the circuit level of the system. We present the crucial noise contributors, calculate the noise level and present optimisation methods to accommodate the best noise performance in readout circuits. The noise contribution of the input amplification stage to the overall system noise performance is treated in detail. The designer’s alternative choices regarding the input capacitance scaling (device level) and the feedback resistance (circuit level) are properly investigated. Other issues such as signal filtering and mixed signal design are also addressed.     

Concurrent discrete event-driven simulation tools

Parallel processing techniques that may enhance the performance of simulation methods for telecommunications networks are reviewed. The assumption that each processor runs a single network component process is avoided, such a premise being unrealistic when simulating large networks. Performance issues arising from implementing distributed simulation strategies on message-passing processor architectures are discussed. Nontrivial network models are separated into domains, each sited on a distinct transputer. Problems arising from the limited connectivity of the transputer are also addressed     

The current status and future prospects of kesterite solar cells: a brief review

Kesterite‐based solar cells are attracting considerable attention in recent years, owing to the reduced toxicity and greater abundance of their constituent elements. In this brief review, we discuss the current status of this important technology by focusing on three key aspects of the device: (i) the interface between the kesterite absorber and the Mo back contact, (ii) the kesterite absorber bulk defects and grain boundaries and (iii) the interface between the kesterite absorber and the buffer layer. By identifying key issues to be addressed, we provide suggestions for their potential improvement and future research. Copyright © 2016 John Wiley & Sons, Ltd.     

A Multi Recipient Aggregate Signcryption Scheme Based on Elliptic Curve

The concept of Internet of bio-nano thing (IoBNT) arose from the need for Biological nanomachines to interconnect intra-body nanonetwork with the cyber Internet aiming to exchange information. However, while numerous studies have focused on communication efficiency among the nanodevices in a given network, challenges such as the IoBNT security, and the interface connection between the nanonetwork and the Internet are yet to be addressed. Thus, in this study, we propose a privacy scheme working on the top of the biocyber interface in the IoBNT paradigm. The proposed chaotic-system is based on the command signal coming from medical personnel to biocyber device embedded on the human body wherein a masked version of feature generated by applying modified Logistic map for increasing the privacy of the human life and released the exact dose. Additionally, the proposed scheme includes BPSK modulation and feature extraction with zero crossing rate. Finally, the privacy scheme increases the key space, thereby ensuring that the right dose is released and the privacy of human life is achieved. The performance analysis of the proposed scheme is presented firstly, by evaluating the proposed privacy scheme working on the top of biocyber interface device by using receiver operating characteristics curve and bit error rate. Then, we study the performance proposed scheme by employing the compartmental models in the forward and reverse biocyber interface of the IoBNT paradigm. The simulation results of the developed model reveal that the proposed IoBNT-based the privacy scheme can enhance the delivery of therapeutic drugs to the target cells while maximizing the privacy issues.

     

A two-dimensional simulation of organic transistors

In this paper, we analyze the operation of organic thin-film transistors (TFT's) using two-dimensional (2-B) numerical simulation to: (1) validate the use of simple MOSFET theory to describe the above-threshold behavior; (2) clarify the subthreshold characteristics, and short-channel effects; and (3) illustrate the operation of organic bilayer devices. Our analysis clarifies a number of issues that can help in device design. We also point out differences between the material parameters used in Si-MOSFET and organic FET simulation, and discuss the circumstances under which a semiconductor device simulator can be used for the simulation of organic transistors     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

The state of the art of electrostatic discharge protection:physics, technology, circuits, design, simulation, and scaling

This paper discusses state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies. ESD physics, semiconductor process issues, device and circuit simulation, circuits, and devices are examined     

Efficient and accurate use of the energy transport method in devicesimulation

Important questions in the application of the highly efficient energy transport method for electron device simulation are addressed by comparing an energy transport calculation with a Monte Carlo calculation used as a control. It is shown that, to calculate average electron energy, it is necessary to incorporate velocity overshoot at certain points in device simulations. Further, energy relaxation times must be taken as functions of energy and may be used as a vehicle for compensation for the neglect of backscattering of cold electrons in regions where energy is rapidly changing. Finally, incorporation of the heat flow vector appears to be unnecessary in the cases studied     

Study of the Band-to-Band Tunneling Hot-Electron (BBHE) Programming Characteristics of p-Channel Bandgap-Engineered SONOS (BE-SONOS)

The band-to-band tunneling hot-electron (BBHE) programming characteristics of the 2 bit/cell p-channel bandgap-engineered silicon-oxide-nitride-oxide-semiconductor (SONOS) (H. T. Lue, et al., in IEDM Tech. Diag., p. 331) device are extensively studied. The lateral BBHE profile is extracted by fitting the experimental current-voltage (I-V) characteristics with 2-D simulation. The results suggest that, after BBHE injection, the local channel potential barrier is reduced, which, in turn, raises the Vt of the p-channel device. The 2 bit/cell operation methods and second-bit effect (2 bit interaction) are examined. The effects of channel-length scaling, junction profile, and effective oxide thickness of the gate stack are also addressed