SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

SiO_2/SiC界面陷阱对SiC MOSFET开关损耗的影响

位于SiO_2/SiC界面处密度较高的陷阱,不仅俘获SiC MOSFET沟道中的载流子,而且对沟道中的载流子形成散射、降低载流子的迁移率,因而严重影响了SiC MOSFET的开关特性。目前商业化的半导体器件仿真软件中迁移率模型是基于Si器件开发,不能体现SiO_2/SiC界面处的陷阱对沟道中载流子的散射作用。通过引入能正确反映界面陷阱对载流子作用的迁移率模型,利用半导体器件仿真软件研究了界面陷阱对SiC MOSFET动态特性的影响。结果表明,随着界面陷阱密度的增加,SiC MOSFET开通过程变慢,开通损耗增加,而关断过程加快,关断损耗减小;但是由于沟道载流子数量的减少、导通电阻的增加,总损耗是随着界面陷阱密度的增加而增加。     

氮离子注入提高4H-SiC n-MOSFET沟道迁移率的分析（英文）

氮离子注入提高4H-SiC MOSFET的沟道迁移率来自两方面的原因:一是减小了界面态密度,另一个是反掺杂。本文详细研究了这两方面的原因。结果表明,当氮的反掺杂浓度和P型衬底的掺杂浓度可以相比较的时候,氮离子注入提高4H-SiC MOSFET的迁移率来自于界面态密度的减小;随着反掺杂浓度的增加,反掺杂在氮离子注入提高沟道迁移率的贡献越来越多,同时,在这种情况下,限制沟道迁移率的机制是表面粗糙度散射。     

SiC-MOS界面优化的工艺验证及MOSFET电学特性仿真拟合

SiC因其优越的电学特性,已发展成为高压功率器件领域的翘楚。然而,SiC与SiO₂界面存在高密度界面态,使得SiC MOSFET沟道迁移率远低于SiC材料本身的体迁移率,大大约束了SiC材料本身电学性能的发挥。为改善反型层沟道迁移率,不同功率器件厂商采用了不同的栅极氧化工艺,所实现的栅极氧化层界面态密度各有不同,现有的功率器件仿真软件提供的多种界面态能级分布模型都需要芯片厂商实际的流片数据作为支撑,这对功率器件上游设计人员产生了阻碍。基于此,文章通过流片测试数据,结合TCAD仿真软件给出了一种用于SiC MOSFET器件仿真的界面态能级分布模型。利用给出的界面态能级分布模型,与实际产品对比,仿真得出的I-V曲线与测试曲线基本重合。     

杂质非完全离化对SiC n-MOSFET电特性的影响

文章研究了SiC中杂质非完全离化对器件性能的影响.通过考虑场致离化效应,分析了空间电荷区电荷密度与表面势的关系,得出在SiC MOSFET反型条件下,可近似认为杂质完全离化.在此基础上,模拟了4H-SiC MOSFET的漏电流-栅压曲线和迁移率-栅压曲线.模拟结果与实验数据非常吻合.     

SiO_2/SiC界面对4H-SiC n-MOSFET反型沟道电子迁移率的影响

提出了一种基于器件物理的4 H- Si C n- MOSFET反型沟道电子迁移率模型.该模型包括了界面态、晶格、杂质以及表面粗糙等散射机制的影响,其中界面态散射机制考虑了载流子的屏蔽效应.利用此模型,研究了界面态、表面粗糙度等因素对迁移率的影响,模拟结果表明界面态和表面粗糙度是影响沟道电子迁移率的主要因素.其中,界面态密度决定了沟道电子迁移率的最大值,而表面粗糙散射则制约着高场下的电子迁移率.该模型能较好地应用于器件模拟.     

SiC JFET与SiC MOSFET失效模型及其短路特性对比

建立了两种碳化硅（SiC）器件JFET和MOSFET的失效模型.失效模型是在传统的电路模型的基础上引入了额外附加的泄漏电流,其中,SiC JFET是在漏源极引入了泄漏电流,SiC MOSFET是在漏源极和栅极引入了泄漏电流;同时,为了体现温度和电场强度与失效的关系,用与温度和电场强度相关的沟道载流子迁移率代替了传统电路模型所采用的常数迁移率.有关文献的实验结果和半导体器件的计算机模拟（Technology Computer Aided Design,TCAD）验证了两种SiC器件失效模型的准确性.所建立的失效模型能够对比SiC JFET和SiC MOSFET的短路特性.     

耗尽型4H-SiC埋沟MOSFET器件解析模型研究

建立了基于漂移扩散理论的4H-SiC埋沟MOSFET器件的物理解析模型。SiC/SiO_2界面处的界面态密度及各种散射机制都会导致器件载流子迁移率的下降,采用平均迁移率模型,分析散射机制对载流子迁移率的影响,讨论了界面态对阈值电压的影响。考虑到器件处在不同工作模式下,沟道电容会随栅压的变化而改变,采用了平均电容概念。器件仿真结果表明:界面态的存在导致漏极电流减小;采用平均迁移率模型得到的计算结果与实验测试结果较为一致。     

O2+CHCCl3氧化对6H-SiC MOS电容界面特性的改善

采用新颖的干O2 CHCCl3(TCE)氧化工艺，制备了P型和N型6H—SiCMOS电容器，并与常规热氧化工艺以及氧化加NO退火工艺进行了对比实验。结果表明，O2 TCE氧化不仅提高了氧化速率，而且降低了界面态密度和氧化层有效电荷密度，提高了器件可靠性。可以预测，O2 TCE氧化与湿NO退火相结合的工艺是一种有前途的制备高沟道迁移率、高可靠性SiCMOS—FET的栅介质工艺。     

基于平均迁移率模型的SiC埋沟MOSFET Ⅰ-Ⅴ特性

提出了一种SiC隐埋沟道MOSFET平均迁移率模型,并在此基础上对器件I-V特性进行了研究。采用一个随栅压变化的平均电容公式,并用一个简单的解析表达式来描述沟道平均迁移率随栅压的变化关系。计算漏电流时考虑了埋沟器件的三种工作模式,推出了各种工作模式下的漏电流表达式,并用实验值对模型进行了验证。     

Excellent effects of hydrogen postoxidation annealing on inversionchannel mobility of 4H-SiC MOSFET fabricated on (112¯0) face

Effects of hydrogen postoxidation annealing (H₂ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112¯0) face have been investigated. As a result, an inversion channel mobility of 110 cm²/Vs was successfully achieved using H₂ POA at 800°C for 30 min. H₂ POA reduces the interface trap density by about one order of magnitude compared with that without H₂ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H₂ POA. In addition, 4H-SiC MOSFET with H₂ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm²/Vs     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.     

Characterization of inversion and accumulation layer electrontransport in 4H and 6H-SiC MOSFETs on implanted P-type regions

The silicon carbide double implanted vertical MOSFET (SiC DIMOS) is a promising candidate for high power switching applications due to the absence of high electric field corners and compatibility with planar IC technology. In this work, we report on the channel mobility behavior in 4H and 6H-SiC MOSFETs fabricated with a low thermal budget process sequence, on implanted p-type regions which mirror the lateral carrier transport region in the DIMOS device. Channel mobilities are higher by an order of magnitude in 6H-SiC compared to 4H-SiC MOSFET's suggesting the 6H-SiC polytype is better suited for fabricating the DIMOS structure in spite of the superior vertical bulk conduction in 4H-SiC. Moreover, channel mobility on accumulated surfaces is higher than values obtained on inverted surfaces. A strong correlation between the observed threshold voltages and channel mobilities is consistently explained by a modified MOSFET conductance formulation in the presence of slowly decaying bandtail states toward the SiC band edges     

Significantly improved performance of MOSFETs on silicon carbideusing the 15R-SiC polytype

Recent studies regarding MOSFETs on SiC reveal that 4H-SiC devices suffer from a low inversion layer mobility, while in 6H-SiC, despite a higher channel mobility the bulk mobility parallel to the c-axis is too low, making this polytype unattractive for power devices. This work presents experimental mobility data of MOSFETs fabricated on different polytypes as well as capacitance-voltage (C-V) measurements of corresponding n-type MOS structures which give evidence that the low inversion channel mobility in 4H-SiC is caused by a high density of SiC-SiO₂ interface states close to the conduction band. These defects are believed to be inherent to all SiC polytypes and energetically pinned at around 2.9 eV above the valence band edge. Thus, for polytypes with band gaps smaller than 4H-SiC like 6H-SiC and 15R-SiC, the majority of these states will become resonant with the conduction band at room temperature or above, thus remarkably suppressing their negative effect on the channel mobility. In order to realize high performance power MOSFETs the results reveal that 15R-SiC is the best candidate among all currently accessible SiC polytypes     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.