Simulations of diffusion barrier deposition on porous low-k films

Implementation of Cu/low-k in advanced interconnections requires a diffusion barrier to prevent copper penetration in low-k dielectrics. The barrier should be continuous to prevent copper diffusion and thin enough to keep interconnection line resistance low. Deposition of a diffusion barrier becomes an issue when porous low-k dielectrics are used. We developed a Monte Carlo simulation model to describe deposition of a diffusion barrier on a porous low-k film. The model provided explanation for the sealing behavior of different porous film by TaN diffusion barrier. Previously we have shown that TaN barrier integrity depends on chemical nature of the substrate rather than on porous structure: the same barrier can be continuous on oxycarbide (SiOCH) but non-continuous on HSQ (hydrogen silsesquioxane) although porous structures of the two films are similar. Using the model, we show that surface diffusion of TaN during deposition plays a key role in continuous barrier formation. Presence of carbon suppresses TaN diffusion (probably by TaC formation) and the barrier does not penetrate deep into the film forming a continuous layer on the top surface. The model is also able to predict sealing behavior for different porous low-k films with different porosity/pore sizes.     

New solutions for intermetal dielectrics using trimethylsilane-based PECVD processes

Trimethylsilane, (CH₃)₃SiH, is a non-pyrophoric organosilicon gas. This material is easily used to deposit dielectric thin films in standard PECVD systems designed for SiH₄. In addition to deposition of standard dielectrics (e.g. SiO₂), trimethylsilane can be used to deposit reduced permittivity (low-k) dielectric versions of amorphous hydrogenated silicon carbide and its oxides. The low-k carbides (k<5.5) are highly insulating and useful as hard masks, etch stops and copper diffusion barriers. The low-k oxides (2.6<k<3.0) are useful as intermetal dielectrics, and exhibit stability and electrical properties which can meet many specifications in device fabrication that are now placed on SiO₂. This paper reviews PECVD processing using trimethylsilane. Examples will show that the 3MS-based dielectrics can be used in place of SiH₄-based oxides and nitrides in advanced device multilevel metal interconnection schemes to provide improved circuit performance.     

A selective CMP process for stacked low-k CVD oxide films

A chemical mechanical polishing process for a stacked low-k dielectric material, which is suitable for inter-metal dielectric applications, has been developed. The dielectric is deposited by CVD and composed of a methyl-doped silicon oxide (i.e., low-k Flowfill) embedded between thin SiO₂ layers. A new CMP parameter is introduced, which is the removal rate selectivity between two different kinds of materials. We were able to adjust the selectivity between cap and low-k Flowfill layer in a range between 3:1 and 1:5 by tuning the slurry mixture. Different test structures were used to investigate the effect of the removal rate selectivity on the planarisation efficiency of the CMP process. A higher removal rate of the low-k Flowfill layer in comparison to that of the cap layer results in a significant increase of the planarisation length and a reduction of the overpolish needed to achieve planarity.     

Thermal conductivity of ultra low-k dielectrics

The so-called 3ω measurement technique (transient hot wire method) was established to determine the thermal conductivity of thin films. Measurements of standard substrates and films validate the found thermal conductivity values and agree with published, commonly accepted values. The method was successfully applied to determine the thermal conductivity of porous low-k dielectric materials using special test structure fabrication. The thermal conductivity of the porous low-k dielectrics thus measured is only between 7 and 13% of the thermal conductivity of thermally grown silicon dioxide.     

On the Homogenization of Multilayered Interconnect for Interfacial Fracture Analysis

The interface crack problem for Cu/low-k interconnect is considered using global-and-local finite element analysis. In the global analysis the thin film interconnect is represented by a homogenized layer with equivalent material properties. Local model around the interface crack tip is analyzed with displacement boundary condition extracted from the global modeling result to determine the fracture mechanics parameters. It is shown that, for the global-and-local modeling approach, interconnect homogenization using representative volume element (RVE) approach provides accurate prediction on the fracture mechanics parameters for an interface crack under either thermal or mechanical loads, while significant error occurs when the interconnect, even though having thickness less than 1/100 of the whole component thickness, is neglected in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal excursion is also investigated as an application example of the global-and-local modeling approach.     

Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Copper metallization for advanced IC: requirements and technological solutions

Due to the scaling down, the contribution of interconnects should become preponderant for the performance of IC. The use of low-k dielectrics and/or low resistivity metals in order to decrease the parasitic capacitance of interconnect is a technological requirement. Especially the use of copper, with mineral dielectric as IMD, instead of aluminium alloy is now commonly accepted. In this paper we compare the intrinsic performance of two damascene architectures. The planarization by metal CMP, which will determine the final metal thickness, may induce killer defects (shorts between lines) or degraded metal sheet resistance uniformity for multi-level metallization devices. The impact on electromigration of the damascene structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent. On the other hand, the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition.     

A photo-oxidation generated low-k dielectric film deposited by reactive evaporation of SiO

A non-stoichiometric silicon oxide film has been deposited by evaporating SiO as a source material in Ar and O₂ mixed gas. The film is composed of SiO and SiO₂, and has a porous structure. The SiO₂ results from some part of SiO reacting with O₂ and its amount depends on the pressure in the chamber. The residual SiO in the film can be photo-oxidized into SiO₂ by ultraviolet radiation with a Hg lamp. The dielectric constant of the film after photo-oxidation is 1.89±0.04 (at frequency of 1 MHz), which shows that this porous structure film is promising for potential application as a low-k dielectric.     

Low-k dielectrics: a non-destructive characterization by infrared spectroscopic ellipsometry

An infrared spectroscopic ellipsometer devoted to the characterization of silicon microelectronics has recently been developed at SOPRA. Its main feature is the ability to measure on a small spot (80×200 μm) with a high signal/noise ratio. An original patented optical design suppresses back face reflection and ensures good-quality spectral measurements in the 600–7000 cm⁻¹ range. The excellent signal/noise ratio allows the performance of measurements in less than 30 s. Automation and real-time analysis are included to offer an operator-orientated metrology tool. Details of the instrument are presented, and its use for the characterization of different kinds of low-k dielectrics.     

TiN-CVD process optimization for integration with Cu-CVD

Integration of Cu-CVD as metallization for on-chip interconnect requires an efficient barrier to avoid any Cu diffusion in the insulating material. These barriers must also promote adhesion of Cu to the inter- and intra-metal level material, and have low resistivity to minimize level to level contact resistance. This paper discusses about the performance of Cu-CVD via integrated with TiN-CVD barrier in Cu/SiO₂ interconnection structures. After a review of the TiN-CVD performance as a diffusion barrier, Cu-CVD adhesion properties will be evaluated as a function of both TiN and Cu deposition process and TiN surface treatments. In addition to the standard tape test method, wettability after annealing of a thin Cu-CVD film deposited on the TiN barrier was studied to characterize adhesion of Cu-CVD to the barrier under evaluation. The presence of fluorine and fluorinated compounds were observed at the Cu/TiN interface, due to Cu-CVD deposition process based on Cupraselect. The major impact of such contamination on adhesion and TiN barrier resistivity will be evidenced. Finally, electrical results are given for two-level Cu interconnections performed in a dual damascene architecture. Very low via chain resistances are obtained after optimization of the TiN-CVD/Cu-CVD process integration.     

Properties of GaAs alloy diodes

GaAs p⁺n alloy diodes have been developed which look attractive as varactors and high speed switches. The forward current in these diodes, which varies with voltage as exp(q V/nkT) where n is nearly one, is neither a simple diffusion current nor due to recombination in the space charge region. It can, however, be explained if one assumes that the alloyed junction is a metal-semiconductor (Schottky) barrier with a metal-semiconductor work function of 0·95 V, or if one assumes that in the alloyed region the band gap of the GaAs has been reduced to less than 1·0 V. The absolute value of the current, its temperature dependence, as well as its voltage dependence can be explained by either of these two models. Since in both these models the current is injected from the n-type base region, the lack of injection luminescence and the extremely short switching times can also be explained. Because there is no direct evidence for the reduction in band gap, the Schottky barrier model seems the more likely explanation. While these diodes may be attractive, the presence of this type of forward currents in GaAs transistors and GaAs tunnel diodes would be deleterious and may explain experimental results in these devices.     

The use of generalised models to explain the behaviour of ohmic contacts to n-type GaAs

The use of two generalised carrier transport models to account for the N_D⁻¹ dependence of the specific contact resistance (ρ_c) of metal-semiconductor Ohmic contacts to n-type GaAs is proposed. Both models include the effects of thermionic emission and diffusion across the high-low barrier junction a priori. Calculations of ρ_c, and comparison with experimental data, show conclusively that thermionic emission is the dominant transport mechanism across the barrier. It is stressed that these models do not rely on prior choices of either of the transport processes. These conclusions are arrived at a posteriori.     

InGaP/GaAs multiquantum barrier structures prepared by low-pressure organometallic vapor phase epitaxy

An InGaP/GaAs superlattice with multiquantum barrier (MQB) effect was demonstrated by low-pressure organometallic vapor phase epitaxial technique. Two types of n-i-n tunnel diodes with either InGaP/GaAs MQB barrier or bulk InGaP barrier were fabricated for comparison. The current-voltage characteristics show that the turn on voltage in the MQB barrier sample is higher than that in the bulk barrier sample. The experimentally measured effective barrier height of the MQB is about 1.8 times that of the bulk barrier, and this value is in quite good agreement with the value, 1.93, theoretically calculated by the transfer matrix method.     

Impact of LKD5109™ low-k to cap/liner interfaces in single damascene process and performance

The importance of interface quality in the single damascene integration process of LKD5109™ porous low-k films is investigated. A strong correlation is observed between chemical mechanical planarization (CMP) performance and LKD/cap layer interfacial fracture energies. The use of FF02™ as cap layer material (an on-purpose developed spin-on organic hard-mask) on LKD leads to superior interfacial adhesion and metal continuity yield as compared to the use of chemical vapour deposition SiC:H cap films. The adhesion quality of LKD/liner films appears less critical than LKD/cap layer adhesion as far as CMP performance is concerned. Electrical line-to-line performance is not always directly correlated with adhesion but rather, more generally speaking, with interface quality (i.e., presence of defects/dangling bonds or moisture). The introduction of surface pre-treatments to enhance interfacial adhesion leads to degradation in both leakage current and breakdown field behaviour because of damage induced at the interface.     

Cu contact on NiSi substrate with a Ta/TaN barrier stack

The thermal and electrical stabilities of Cu contact on NiSi substrate with and without a Ta/TaN barrier stack in between were investigated. Four-point probe (FPP), X-ray diffraction (XRD), scanning electron microscopy (SEM), depth-profiling X-ray photoelectron spectroscopy (XPS), and Schottky barrier height (SBH) measurement were carried out to characterize the diffusion barrier properties. The SBH measurement provides a very sensitive method to characterize the diffusion barrier properties for the copper contact on NiSi/Si. The results show that the Ta/TaN stack can be both thermally and electrically stable after annealing at 450 °C for 30 min and it will have a potential application as a diffusion barrier for Cu contact on NiSi.     

非晶硅少子扩散长度的测量

正 (一)引言 非晶硅少子扩散长度对非晶硅太阳电池的性能有重要影响,它是表征非晶硅材料质量的重要参数。最近Dresner和Moore分别用表面光电压法(SPV法)测量非晶硅少于扩散长度获得成功。但前者需要超高真空系统,样品表面要经过溅射和退火,后者使用非晶硅液体肖特基势垒,装置较烦。我们试用顶层淀积了金属镍的非晶硅薄膜作样品,利用镍和非晶硅膜构成的金属肖特基势垒进行表面光电压测量,获得成功。这样     

Thermomechanical property of diffusion barrier layer and its effect on the stress characteristics of copper submicron interconnect structures

Thermal stresses of thin titanium nitride (TiN) films on Si and Ge substrates have been measured by the bending beam method. The biaxial modulus and coefficient of thermal expansion of TiN thin film were deduced from the thermal stress data and found to be 355 GPa and 7.4 ppm/°C, respectively. Finite element analysis was used to study the effect of TiN diffusion barrier on the stress state of Cu lines in submicron damascene interconnects. The diffusion barrier was found to have a significant effect on the stress state of the Cu lines, especially for those embedded in interlevel dielectrics of low dielectric constant (k) materials. For the Cu/oxide interconnect structure, the metal lines with diffusion barrier were found to have a high near-hydrostatic triaxial stress state as expected. For the Cu/low k interconnect structure, a near-hydrostatic stress state was found to exist in the presence of the diffusion barrier; without the diffusion barrier, the stress state was not near-hydrostatic, instead it was dominated by a shear behavior. The implication of the diffusion barrier effect on the thermomechanical reliability of Cu interconnects is discussed.     

Comparison of Thai''s theory with experimental boron doping profiles in silicon, diffused from boron nitride sources

Silicon wafers, (111)-oriented, were diffused with BN sources at temperatures form 986 to 1132°C and times from 15 min to 4 hr at various flow rates of ambient gas (N₂) of 2–80 1/hr. Doping profiles were determined. They showed plateaus of nearly constant doping concentration near the silicon surface and great deviations from erfc profiles. From this profiles diffusion coefficient D(c) was derived by means of Boltzmann's method as a function of doping concentration C. Comparison with Thai's theory (corrected by Jain and van Overstraeten) shows for the nondegenerate case of field-enhanced diffusion good agreement with the experimental results of D(c). A remarkable increase for D(c) is found for boron concentrations C≥10¹⁹ cm⁻³. Preexponential term D₀ activation energy E_A for diffusion coefficient D(c) are derived and found to be 1.36 cm²/sec and 3.59 eV respectively. They coincide well with values given by other authors.     

非晶硅肖特基太阳电池的I-V特性分析

本文提出了一种在光照和短路条件下测量Ni/-Si∶H肖特基结势垒宽度的方法。同时,又在实验确定的参数的基础上,从理论上计算了在AM1太阳光谱照射下Ni/-Si∶H太阳电池的I-V曲线。由此得到的非晶硅少子扩散长度的数值与作者1983年用表面光电压法(SPV)测得的是一致的。从计算结果出发,着重分析了影响填充因子的各种因素。与实验对比可以得出结论:被测太阳电池的填充因子小是串、并联电阻造成的,而不是扩散长度太短的缘故。     

Resonant tunneling through magnetic edge states

Resonant magneto-tunneling of electrons through AlGaAs/GaAs/AlGaAs double barrier structures is investigated for samples with different quantum well widths (300–800Å) and barriers (130–200Å). In a strong transverse magnetic field, resonant tunneling is quenched, and a new set of resonances appear at low bias. These resonances are interpreted as due to tunneling between the edge states on either side of the first barrier. The edge states are the quantum mechanical analog of the classical skipping orbits.