A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

Injection-coupled memory: A high-density static bipolar memory

The design of a new static bipolar memory comparable with dynamic FET storages in density, but superior in performance and power dissipation is discussed. The concept of direct minority carrier injection is utilized for both the cell current supply and the coupling to the read/write lines. This has led to an extremely high degree of device integration resulting in a cell size of 3.1 mil/SUP 2/ using a standard buried layer process with 5-/spl mu/ line dimensions and single layer metallization. Investigations on exploratory chips containing small arrays have fully verified the feasibility. The cells have been operated at an extremely small d.c. standby power of below 100 nW. For a 4K b chip of about 160/spl times/150 mil/SUP 2/, an access time around 50 ns can be projected from the measurements simulating a 64/spl times/64 bit array. An extrapolation of the memory cell layout with oxide isolation and self-aligned N/SUP +/ contacts has resulted in a 1.1-mil/SUP 2/ cell with 5-/spl mu/ line dimensions.     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

A 200-mW GaAs 1 K SRAM with 2-ns cycle time

A very high-speed and low-power 1024/spl times/1 SRAM has been designed and fabricated using a normally-off recessed-gate FET technology. Minimum gate length is 0.7 /spl mu/m. A minimum access time of 1.4 ns has been obtained with a power dissipation of 210 mW. The memory cell area is 1197 /spl mu/m/SUP 2/ and the chip size is 1.91/spl times/2.21 mm/SUP 2/. The output voltage swing across a 50-/spl Omega/ load is 700 mV. The maximum simulated yield for 1 K SRAMs is discussed theoretically. A mean standard deviation in threshold voltage less than 15 mV is required to obtain 100% design yield. The SRAM has been shown to be fully operational using the march and checkerboard tests and exhibits read and write cycle times of 2 ns.     

A 16 DIP, 64 kbit, static MOS-RAM

A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW.     

A 288K CMOS pseudostatic RAM

A 288-kb pseudostatic RAM with high density and ease of use has been fabricated using polycide-gate n-well CMOS technology. For high speed and low power dissipation, a half-V/SUB cc/ precharging scheme, with CMOS back biased to V/SUB BB/, was used. For easier use, an address transition detector, plus auto-refresh and self-refresh, were adopted. Organized as 32K/spl times/9 bits, the RAM occupies an area of 55 mm/SUP 2/ and has a cell size of 6.8/spl times/13.6 /spl mu/m/SUP 2/, which was achieved using the 2-/spl mu/m design rule. A typical address access time is 125 ns, and the operating current is 60 mA at a 125-ns cycle time. Standby power is 2 mA.     

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.     

A 0.85-ns 1-kbit ECL RAM

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 /spl mu/m and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 /spl mu/m in the first layer and 6 /spl mu/m in the second one. The chip size is 2.5/spl times/2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.     

A 1.0-ns 5-kbit ECL RAM

A bipolar 512/spl times/10-bit emitter-coupled logic (ECL) RAM with an access time of 1.0 ns and a power dissipation of 2.4 W, achieving an access-time power/bit product of 0.48 pJ/bit, has been developed. The RAM was fabricated using an advanced bipolar technology featuring poly-base self-alignment, poly-emitter shallow profile, and silicon-filled trench isolation with a minimum mask dimension of 1.2 /spl mu/m. A Schottky-clamped multiemitter cell with a cell size of 760 /spl mu/m/SUP 2/ is obtained as a result of compact cell layout and the use of 1.2-/spl mu/m trench isolation.     

A high-speed 16-kbit n-MOS random-access memory

This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of 200 ns) with low-power dissipation (600 mW at the 400-ns cycle time). The fully decoded memory is fabricated on a 5/spl times/7 mm/SUP 2/ chip and is assembled in a 22-lead ceramic dual-in-line package.     

A 45-ns 256K CMOS static RAM with a tri-level word line

A 32K words by 8-bit static RAM fabricated with a CMOS technology is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1.3-/spl mu/m design rule allowed layout of the NMOS memory cell in an area of 116.0 /spl mu/m/SUP 2/ and the die in 49.6 mm/SUP 2/.     

13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

The development is discussed for a 13-ns, 500-mW, 16K word/spl times/4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS) technology that combines a bipolar and a CMOS device on the same chip. The power dissipation of the RAM is about one half that of the conventional 64-kb bipolar ECL RAM. This high-speed, low-power RAM has been realized through a concept of a MOS-type memory cell, bipolar circuits, and a CMOS combination gate to allow for increased LSI integration.     

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.     

A 70 ns high density 64K CMOS dynamic RAM

A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.     

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.     

A 1024-bit MNOS RAM using avalanche-tunnel injection

MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.     

SNOS 1K/spl times/8 static nonvolatile RAM

Using an advanced n-channel, double level polysilicon SNOS technology, a 1K/spl times/8 bit nonvolatile static RAM has been designed. Typical RAM access time is 300 ns, with typical active power dissipation of 300 mW, and standby power of 160 mW. Endurance of 10/SUP 4/ erase/store cycles has been demonstrated. The ability to measure erased and written memory thresholds allows prediction of retention lifetime. For the 8K NVRAM, the minimum retention lifetime is 1 year following a 10 ms erase and store.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

An MSI GaAs integrated circuit: 4 bit arithmetic and logic unit

A GaAs 4 bit arithmetic and logic unit (ALU) has been fabricated using a planar ion implantation technique with 2 /spl mu/m gate length FETs. The basic circuit is a buffered FET logic (BFL) circuit composed of normally on GaAs MESFETs and Schottky diodes. The active layers of the FETs and diodes are made by implanting Si into Cr-doped semi-insulating GaAs substrate. This ALU contains 629 FETs and 225 diodes within an area of 1.6/spl times/2.1 mm/SUP 2/. The ALU, capable of driving 50 /spl Omega/ transmission lines, is mounted on a 24 lead flat package. A delay time of 2.1 ns through the data path and a total power dissipation of 1.2 W with supply voltages of +5 V and -3 V have been obtained.