GaAs E/D MESFET 1-kbit static RAM fabricated on silicon substrate

A GaAs enhancement/depletion (E/D) MESFET 1-kbit static RAM has been fabricated on a 2-in GaAs-on-Si substrate. This is the most complex GaAs circuit reported to date for GaAs-on-Si material. The GaAs layer is grown on a     

A GaAs 16-kbit static RAM using dislocation-free crystal

A GaAs 16-kbit static RAM was developed using high-density integration technology and high-uniformity crystal. Highly integrated SAINT FET's with 1.0-µm gate length and 1.5-µm interconnection lines were formed by self-alignment and fine photolithography. Highly uniform crystal with less than 20-mV threshold scattering was obtained from an In-doped dislocation-free LEC with a 2-in diameter. An address access time of 4.1 ns was obtained with an associated power dissipation of 1.46 W.     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

A fully operational 1-kbit HEMT static RAM

In this paper we describe the current status of materials and fabrication technologies, and optimal design of a memory cell, and the performance of fully functional 1-kbit HEMT SRAM's. The surface defect density on MBE-grown wafers has been reduced to less than 100 cm^-2by improving MBE technology. Standard deviations of threshold voltages are 6.7 and 11.8 mV for enhancement-type and depletion-type HEMT's, respectively, measured in a 10 mm × 10 mm area. These deviations are sufficiently small for DCFL circuits. Memory cell design parameters have been optimized by circuit simulation, where the effects of variations in threshold voltages are taken into account. Full function of 1-kbit SRAM's has been confirmed by marching tests and partial galloping tests. The RAM chips have also shown excellent uniformity in access time. The difference between maximum and average values on the RAM chip is 4 percent.     

An asynchronous GaAs MESFET static RAM using a new current mirrormemory cell

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm² and cell current of 60 μA were achieved using a conventional E/D process     

A high-speed 1-kbit high electron mobility transistor static RAM

A 1-kbit static RAM with enhancement and depletion-mode devices was designed and fabricated using the high electron mobility transistor (HEMT) technology. The RAM circuit was optimized to achieve ultra-high-speed performance. A subnanosecond address access time of 0.6 ns was measured at room temperature for a total power dissipation of 450 mW. The minimum WRITE-ENABLE pulse width required to change the state of memory cell is less than 2 ns on probe testing. The best chip has 3 bits that failed to function, which corresponds to a bit yield of 99.7 percent. According to the simulation, variations of the threshold voltage inside the memory cell greatly reduce its stable functional range. High-speed operation requires more uniform threshold voltage control to achieve fully operational LSI memory circuits.     

Design of GaAs 1k bit static RAM

A 1 k bit GaAs static RAM with E/D DCFL was designed and successfully fabricated by SAINT. A bit line pull-up was introduced to the design to make higher operation speed by 25 percent and reduce cell array power consumption by 50 percent. The RAM circuit was optimized in the points of a speed, a power, and an operating margin. A minimum address access time of 1.5 ns was measured for a total power dissipation of 369 mW. This performance is the best achieved so far, for practical application in cache or buffer memories.     

GaAs 256-bit static RAM

A GaAs 256×1-bit static RAM with 2000 FETs organised in E/D-type DCFL circuits was successfully fabricated. A planar device structure was realised by using selective ion implantation and dielectric intermediate lift-off technology. The access time and the power dissipation were 50 ns and 9.4 mW, respectively.     

A 0.85-ns 1-kbit ECL RAM

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 /spl mu/m and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 /spl mu/m in the first layer and 6 /spl mu/m in the second one. The chip size is 2.5/spl times/2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.     

GaAs 1 kbit static RAM with self-aligned FET technology

A GaAs-1 kbit RAM is demonstrated to realize high-speed switching at the LSI level. The SAINT FET is utilized to eliminate the surface depletion without an increase of excess capacitance. To lower the threshold voltage standard deviation, a one-direction gate arrangement is adopted. A pull-up circuit is also a new addition to the first reported RAM. The resulting RAM performances are 1.5 ns address access time with 369 mW power consumption. The minimum write-enable pulsewidth is less than 2 ns. The maximum number of good bits is 1001 bits/1024 bits. The problems of mass production of GaAs LSI are discussed.     

Estimation of GaAs static RAM performance

A simple and accurate GaAs MESFET model for circuit simulation has been established. Calculated static and dynamic performance have been found to coincide well with experimental results. RAM performance with various FET's was estimated adopting this model for the simulation. Reduction in series resistance by n⁺doping outside a gate and/or shortening source-drain distance is predicted to be very effective in improving not only access time, but also threshold-voltage margin. A 1-kbit static RAM with 0.8 ns at 400-mW dissipation power will be attainable by using a 0.5-µm gate length FET, with an allowable threshold-voltage standard deviation of 80 mV.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

A High-Speed 64-kbit CMOS RAM

The first memory of a high-performance CMOS 64K family, an 8K X 8 asynchronous static RAM, has been developed using a full CMOS six-transistor memory cell approach to reduce power consumption and enhance endurance in disturbed environments. New design techniques have been adopted to optimize both speed and power dissipation. Built on a self-aligned CMOS technology with 1.5-/spl mu/m design rules, the circuit reaches the size of 45 mm/sup 2/ and achieves access times of 35 ns under typical conditions. To improve fabrication yield of the memory, redundancy assistance has been utilized allowing correction of physical defects by column replacement.     

Fully ECL-compatible GaAs standard-cell library

A standard cell library for MSI circuits is described. It is based on buffered FET logic (BFL) with 1-μm gate-length MESFET transistors. It contains gates, buffers, master-slave flip-flops, and ECL interfaces and it has been optimized to operate over the military temperature range. It is fully compatible with ECL circuits (signal level and power supply). Typical propagation delay is 80 ps for an inverter (FI=FO=1) and power dissipation is 5 mW per BFL cell. A realistic printed circuit board for test and demonstration is proposed     

1WKu波段GaAs MESFET

采用新型通孔结构制作的微波功率GaAs FET,在12GHz,输出功率达1.2W,相应功率增益为6.6dB。在15GHz输出功率为1.1W,相应增益为5.5dB,漏极效率大于30％。     

A 3-ns 1-kbit RAM using super self-aligned process technology

A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.     

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.     

An ultrahigh-speed GaAs MESFET operational amplifier

A wide-bandwidth GaAs MESFET operational amplifier is reported, with a 65-dB DC gain and a 20-GHz gain-bandwidth product at 500 MHz. The circuit uses a variety of local feedback techniques to enhance the overall gain. The use of an undoped GaAs buffer, grown at a relatively low temperature (≈300°C), eliminates backgating and light sensitivity. The circuit was fabricated in an 80-GHz f_T MESFET process, with 0.2-μm electron-beam defined gates. The high levels of 1/f noise, MESFET frequency-dependent output conductance, and large offset voltage standard deviation limit the application of the circuit to moderate precision applications