A switching lateral transistor

A switching phenomenon has been reported in certain lateral geometry transistors in silicon integrated circuits. These devices switch between conducting and nonconducting states at a critical value of VCE. A hypothesis for the mechanism has been proposed. In this paper an equivalent circuit is developed for the switching lateral transistor and is used to predict transistor behavior. The effect of manufacturing tolerances on the device switching voltage is investigated and a technique of production control is proposed. Circuits using the device are described in which the circuit switching voltage may be varied over a wide range. Some applications of the switching lateral transistor, as an overvoltage protection circuit and a relaxation oscillator, are described.     

Design, fabrication, and characterization of a germanium microwave transistor

This paper summarizes the design, fabrication, and characterization of a p-n-p planar epitaxial germanium transistor for use as an amplifier in the 1-to 4-GHz frequency range and as a high-speed switch. The analytical basis for the geometry and impurity profile arrived at in the development of this transistor is presented in conjunction with experimental measurements. It is shown that good agreement between experiment and theory can be achieved even in the 1-to 6-GHz frequency region when sufficient attention is given to the formulation of an adequate equivalent circuit. For example, the calculated fTof this germanium microwave transistor is 5.7 GHz, which compares to a typical measured value of 5.6 GHz. The measured maximum available gain of the better transistors is 13.4 dB at 1.3 GHz (the corresponding calculated value is 13.9 dB) with a 2.7-dB noise figure at the same frequency.     

The method of estimating delay in switching circuits and the figure of merit of a switching transistor

A simple method of estimating delay in a switching network is outlined. The simplicity of formulas thus obtained makes them readily applicable for circuit comparisons or device optimization purposes. It is shown that a term involving the product of base resistance and diffusion capacitance forms a major limitation on high-speed, voltage-driven circuits. This method is applicable to a general class of switching problems.     

Two-dimensional computer simulation for switching a bipolar transistor out of saturation

A two-dimensional numerical analysis for the turnoff of a bipolar transistor from high injection level (VBE= 900 mV) is carried out. VBCis being kept constant at 1 V. Distributions of potential, electron, and hole density are interpreted and lead to a subdivision of the total transient time into four time regions, each governed by a single phenomenon. These phenomena are 1) fast discharge of the sidewall transistor, 2) the "lateral wave" which has the dominating influence in the total switching time, 3) the vertical discharge, and 4) the emitter discharge. The transient behavior is essentially ruled by two-dimensional lateral effects. Hence one-dimensional models are not adequate for switching a transistor out of saturation.     

Automatic switching synchronisation of serial and parallelavalanche transistor connections

150 A/10 ns current pulses across a low ohmic resistive load (1 Ω) were obtained using Marx-type serial connection of the stages with the parallel connection of a few avalanche transistors in each stage. The automatic feedback allows perfect time synchronisation of the switching process in all the transistors     

Formal design procedures for pass transistor switching circuits

Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approach. The savings in silicon area depends on the transistor count as well as the interconnect structure. Maximum topograph regularity for an array of pass transistors can be achieved in the intersection of the set of control variables with the set of pass variables in a null set. This allows the pass variables and the control variables to flow at right angles to each other. This requirement may increase the transistor count in the design, hence there is a tradeoff between topological regularity and transistor count. Cells drawn in CMOS and NMOS are compared.     

Profiled current drive for pulsed bipolar transistor switching

Preliminary investigations have been made of the profiling of base current drive to obtain fast turn-on without lifetime pulse stretching and turn-off delays.<>     

Transient Monte Carlo analysis and application to heterojunctionbipolar transistor switching

A self-consistent simulation using the Monte Carlo ensemble particle technique for analysis of heterojunction bipolar transistor (HBT) transient behavior, such as switching performance, is presented. The transient Monte Carlo method has been applied to a self-consistent simulation of two HBT designs with improved collector structures for high-speed and high-frequency applications, and the results are compared with the characteristics of conventional HBTs. The simulation results indicate that the two new collector structures, the inverted field collector and the undoped collector, have better switching performance than the conventional HBT. The study of the switching characteristics' dependence on collector-base bias voltage and collector current suggests that the inverted field HBT is the best approach in terms of switching properties. The results are supported and explained by examining electron transport properties such as overshoot velocity and energy valley occupation, as well as band bending in the collector space-charge region at different current levels     

A silicon medium-power transistor for high-current high-speed switching applications

A diffused base, diffused emitter, n-p-n silicon switching transistor has been developed for high-current applications such as switching magnetic memories. The transistor is designed to operate as a switch at the 0.75- ampere level. For a collector current of 0.75 ampere, the large signal current gain is 20 and the saturation voltage drop 4 volts. The breakdown voltages are 75 volts collector-to-base, and 6 volts emitter-to-base. The unit shows fast switching characteristics. The rise, storage, and fall times are each of the order of 0.1 µsec. It has a common emitter unity gain frequency greater than 50 Mc. The transistor employs a localized emitter produced by photoresist techniques and oxide masked diffusion. Lead attachment is accomplished by compression bonding. The silicon wafer is bonded through a molybdenum intermediary to a massive copper stud. The design theory of the device, and the variation of device characteristics with temperature are given. The applicability of this devices to RF amplifier service is also discussed.     

The SINFET: a new high conductance, high switching speed MOS-gated transistor

A new MOS power semiconductor device with a very low on-resistance and a switching speed comparable to conventional n-channel power MOSFETs is described. The fabrication process is similar to that of an n-channel lateral DMOS transistor but with the conventional high-low `ohmic? drain contact replaced by a Schottky contact. In operation, the Schottky contact injects minority carriers to conductivity-modulate the n- drift region, thereby reducing the on-resistance by a factor of about ten compared with those of conventional n-channel power MOSFETs of comparable size and voltage capability. Furthermore, since only a small number of minority carriers are injected, the device speed is comparable to conventional n-channel power MOSFETs.     

Techniques for reducing the peak power of a switching transistor with p-i-n diode load

Describes techniques for reducing the peak power of switching transistor that reverse biases a p-i-n diode load. Particular emphasis is placed on a parallel combination of a Zener diode and an inductor and it is shown that, for an experimental p-i-n driver, the peak power is reduced from 252 to 90 W.     

Design and manufacture of a microwave low-noise transistor having beam-leads

The design and fabrication technology of a bipolar microwave low-noise transistor with a beam-lead structure is described. The process which we present here has the following advantages: it is simple, it results in a satisfactory device reliability (Ti-Pt-Au metallizations and final passivation by a Si3N4layer), and it can be applied to the finest geometrical structures produced at the present time. The comparison between the results obtained for transistors in the beam-lead configuration and those obtained for packaged transistors clearly shows that microwave transistors can be fabricated with beam-leads with no degradation of the high-frequency performance. For a beam-lead interdigitated structure having four emitters 1.5 µm in width, the performance at 2 GHz was typically:G_{pmax} = 11.2dBN.F._{min} = 3.30dBG_{p}(N.F._{min}) = 9.2dB.     

Optimal characterization of a microwave transistor using grey wolf algorithms

Analog Integrated Circuits and Signal Processing - Modern time microwave stages require low power consumption, low size, low-noise amplifier (LNA) designs with high-performance measures. These...     

On modelling and characterization of single electron transistor

As the nanotechnology rose to the surface, single electron transistor (SET) was invented. In contrast to the well-known response of MOS current, SET current has peaks at certain gate voltages, which disappears at other gate voltages. The SET has promised to be valuable in many applications for its high speed and low power consumption. First, a comparison was drawn between different models of SET based on the orthodox theory. Such theory explains electron transport from source to drain, employing free energies, tunnel rates and coulomb blockade phenomenon, in addition to quantizing electron tunnelling. Afterwards, a simplified model was proposed to account for unnecessary lengthy calculation processes, resulting from the large number of states assumed for simulation. The proposed PSPICE simplified model was confirmed by comparing its results to the results of the available models, and it was found to agree well with them. Taking much less runtime than the available models, the proposed model can easily be used to simulate SET-based integrated circuits on PSPICE.     

Fabrication and characterization of the amorphous-silicon staticinduction transistor

Experimental results for the fabrication and electrical characterization of a hydrogenated amorphous silicon static induction transistor are reported. The I-V measurements demonstrate the triode-like enhancement mode operation of the device and show an on-off current ratio of 300 and a pinchoff voltage of -9.5 V for V_ds=6 V. Numerical simulation suggests that the differences between experimental and theoretically predicted results are due to the presence of a high-density-of-states layer at the a-Si:H/a-Si:H interface     

Fabrication and characterization of a new EEPROM cell with spacer select transistor

In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 /spl mu/m/sup 2/ with 0.18 /spl mu/m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests.     

Fall time characteristics of the Darlington transistor switching an inductive load

In an inductive circuit the fall time delay of a Darlington transistor can be significantly longer than theory predicts. The increase is shown to be related to the rate of rise in collector voltage. By including this effect, a more general expression for fall time is developed.