Concise transient SPICE model for bipolar power transistor quasi-saturation simulation

A concise transient SPICE model is presented in this paper to predict both the static and the switching behaviour of power transistors, with emphasis placed on quasi-saturation effects. The model is proposed to simulate both ohmic and non-ohmic quasi-saturation phenomena by automatically adjusting the hole injection ratio term. The model incorporates the currently used Gummel-Poon (GP) model and an additional charge-control relation for the transistor's epitaxial collector. The turn-off charge removal phenomenon is not modelled specifically; however, the charge-control equation for the epitaxial collector region may partly simulate this effect where the quasi-saturation region is entered. The validity of the model is verified by comparison between the original SPICE bipolar junction transistor model and experimental data for both DC and turn-on conditions. Methods for determining the model parameters are described.     

Collector junction modeling of planar transistors

This work obtains a correlation between the physical structure and capacitance characteristics of collector junctions of planar bipolar epitaxial transistors. It uses an exponential model to represent the impurity distribution and makes available by non-destructive techniques base impurity profile constant, background concentration and collector junction depth from terminal measurements. The methods take care of such aspects of device geometry which are particular to small area high frequency transistors. Procedures are proposed for systematic evaluation of stray and sidewall capacitances. The latter can be used to monitor junction depth. Of interest for quick estimation of parameters is a method that utilises derivatives of the C(V) plot and does not require evaluation of strays.     

The saturation characteristics of n-p-ν-n power transistors

The transport equations and charge-control concepts are applied in an analysis of a static conductivity-modulation mechanism occurring in the collector region of n-p-ν-n power transistors. This results in an expression for collector-emitter saturation voltage as a function of terminal currents and device parameters. An expression is derived which describes the current gain characteristics of saturated epitaxial and triple-diffused devices. The analysis is also used to illustrate the relationship between the emitter metallization resistance, collector charge storage, and the turn-off crowding mechanism experienced by high-frequency saturating transistor switches. An analysis of a time-dependent collector conductivity modulation process is used to derive an expression which describes the repetition frequency dependence of the collector-emitter saturation voltage of an epitaxial (or triple-diffused) transistor switching a square wave of collector current. It is concluded that frequency-dependent edge-crowding mechanisms occur only at much higher frequencies than those considered in this study.     

Determination of a collector junction model for planar bipolar transistors

This paper is concerned with the representation of the collector-base junction of planar bipolar transistors by a model capable of accurate characterization of junction capacitance and avalanche breakdown behavior. The model chosen consists of an exponential impurity density profile with cylindrical peripheral region approximation, and is regarded as the simplest representation suitable for the purpose. Objectives are the practical determination of the defining parameters (collector background, impurity density, exponential characteristic length, and collector junction depth) for such a model, and the demonstration of its accuracy for the physical characterization of the device structure. Model parameter determination is carried out in terms of junction capacitance and BVCBOmeasurements, by processes of computer fitting between model and measured data; the procedures used are nondestructive. It is shown, in particular, that the values obtained for the collector resistivity and junction depth are in very good agreement with those derived by 4-point probe measurement and by bevel and stain sectioning, respectively.     

A compact physical large-signal model for high-speed bipolar transistors at high current densities—Part I: One-dimensional model

A compact physical large-signal transistor model is presented that is suited for simulating high-speed bipolar IC's even if the transistors are operated deeply within the high-current region (including quasi-saturation). Like the well-known and currently used Gummel-Poon model, it is based on the integral charge-control relation (ICCR) proposed by Gummel. However, in the high-current region it shows much better accuracy, especially for high-frequency and switching operation. This is mainly a result of the fact that the transit time (and thus the minority-carrier charge) is chosen as a basic model parameter, which is carefully measured and accurately approximated by analytical expressions throughout the total interesting operating range. In Part I of the work, presented here, the model and its parameters are described for the one-dimensional case. Its validity is verified by comparison with exact numerical transistor simulations of both the dc characteristics and the switching behavior. The simulations are based on doping profiles that are typical of transistors in high-speed IC's. Methods for determination of the model parameters are presented. In Part II [1], the model is extended to the two-dimensional case, i.e., to real transistors. It is experimentally verified by measuring the dc characteristics and the switching behavior of very fast transistors with high transit frequency (fT≈ 7 GHz) and small emitter stripe width. The complete model, which is called HICUM (from "high-current model"), was already implemented in the circuit analysis program SPICE 2.     

Application of a charge-control model to high-voltage power transistors

Basic charge-control concepts are applied to the problem of predicting the static and large-signal switching characteristics of high-voltage transistors, with particular emphasis placed on the quasi-saturation region. Under the assumptions of unity base transport factor and one-dimensional current flow, simple equations for device electrical characteristics are derived in terms of readily determined device parameters. A two-region model is developed for predicting the turn-on process. Measured turn-on waveforms and collector characteristics are compared with the calculated behavior for a BVCE0= 400 V switching transistor. A comparison with hFE(Ic) data is also given for different temperatures. In all cases, good agreement with the predictions of the model is obtained. Implications of the model with respect to device design and characterization are discussed.     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Subnanosecond-pulse generator with variable pulsewidth using avalanche transistors

The letter describes a pulse generator with epitaxial silicon planar transistors working in the avalanche-breakdown mode. The risetime is 150 ps and the fall time 200 ps. The pulse-width can be varied continuously between 0.3 and 120 ns, without changing the maximum amplitude of about 15 V. Simple rules for the exact design of the circuitry are given.     

Experimental study on current gain of BSIT

A means to improve the current gain hFSof the BSIT in a high drain current region has been derived from an experimental study about the dependency of the hFSversus drain current relationship on the channel width, the gate junction depth, and the impurity concentration in the n^-high-resistivity drain region. The BSIT, designed in this manner and including 9000 channels in a chip of 7 × 10 mm², exhibits a current gain over 100 and high switching speeds, a rise time of 200 ns, a storage time of 200 ns and a fall time of 25 ns at a drain current of 50 A.     

RF power transistor storage time: theory and measurements

Measurements on two types of UHF power transistors are given. The measured charge storage time constants (/spl tau//SUB s/) were 89 ns and 173 ns, effectively `infinite' for most applications. Then t/SUB s/ is essentially independent of /spl tau//SUB s/, and depends mainly on circuit properties: base drive and collector current waveforms. The measured dependence of t/SUB s/ on circuit and transistor parameters is in accordance with analytical predictions. Therefore storage time can be accounted for explicitly in a priori circuit design of RF power amplifiers.     

Extended charge-control model for bipolar transistors

In modeling bipolar transistors the charge-control concept provides a means to predict dynamic behavior from a detailed knowledge of the steady state. As such, it is a first-order approximation lacking accuracy. It is shown that a considerable improvement can be obtained when the concept is extended by allowing time delays in the relations between controlling charges and terminal voltages and currents. It suffices to introduce two delays whose magnitudes can be determined or estimated from the steady-state solution. The increased range of validity of the extended charge-control model is demonstrated in detail, by confronting it with a rigorous model and comparing small-signal parameters.     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

Maximum rapidly-switchable power density in junction triodes

The maximum power density which may be switched at (switching time/current gain) quotients comparable to 1/2πfαis shown to be 10⁵- 4 × 10⁵watts/cm²for p-n-p germanium transistors. This result is derived first for junction triodes in which the collector depletion layer at peak reverse voltage lies largely in a collector body of conductivity type opposite to that of the base; e.g., diffused base transistors of the mesa type. The limitation arises from the linear dependence of maximum (scattering limited) current density(J_{max})on collector-body impurity concentration(N_{Ac})and from the approximately reciprocal dependence of breakdown voltage(BV_{CB})on the same parameter. It is shown that space-charge limitation of current dennsity leads to a somewhat lower limit for intrinsic collector barriers of the same maximum width and, a fortiori, to a lower value for collector barriers lying largely in material of the same conductivity type as the base layer. Similar limits for n-p-n germanium and for silicon transistors are higher but generally comparable.     

Space-charge layer width in diffused junctions

This paper outlines a calculation of space-charge layer width in a planar junction made by diffusing an n or p impurity (assumed to follow a Gaussian or a complementary error function distribution) into a uniformly doped crystal of opposite conductivity type. The collector junction of most drift transistors conforms closely to this model. An exponential approximation to the impurity distribution permits curves to be drawn of the space-charge layer penetration in each direction from the junction as a function of applied reverse voltage, and of the electric field distribution. The quantities involved are normalized in terms of the initial doping level N1, the impurity diffusion lengthL = 2 sqrt{Dt}, and the junction depth xj. The curves should be useful in calculating depletion-layer capacitance, transistor punch-through voltage and junction breakdown voltage.     

Transient analysis of lateral transistors for use in CHL circuits

Transient response of the lateral transistor under collector excitation with a constant emitter-base bias has been analyzed using the charge control model. The use of this analysis in the study of the switching behavior of CHL and CHIL circuits is indicated. The similarity of CHL switching with that in I/SUP 2/L circuits is pointed out. The dependence of the rise and storage times of the transistor on collector current has been studied. The storage time is found to decrease with the discharging collector current, whereas the rise time increases with the initial collector current. The storage time can be lower than the rise time. The contribution of the model time constants to the response time constant has been investigated.     

Peak temperature during turnover and the volumetric degradation of switching transistors and IC-s

Temperature increase as a consequence of switch-over power transients can be blamed as the cause of some typically volumetric failures, e.g. C-E punch-through and C-B breakdown, in high-level switching operation. Calculating the depth of thermal penetration on both collector junction sides and considering the thermal capacity of this heated-up volume section as well as the thermal resistance for the same, both as a function of time, one gets a fair model for junction temperature rise estimations, i.e. in the knowledge of switchover power vs time function and constructional data of a transistor one can calculate the junction temperature vs time function. Considering several typical transistors of various technologies ranging from the minute transistor on a monolithic IC chip to bulky alloyed Ge or mesa Si power types and assuming a fair structure and even current distribution, it is proved that the arising peak turnover temperature jumps are completely harmless since they are ranging from some hundredth °C (IC transistor) to some °C (power type) at full rated switching power levels. A badly uneven structure, however, leads to thermal runaway and the occurrence of hot spots in the bulk and so to total deterioration (short) since temperature rise is inversely proportional to the junction area involved in actual current conduction, i.e. to the ratio of effective to nominal junction area, especially at power transistors where specific turnover energy density is high. Thus, brief operational screen tests where collector current limiting ratings are transgressed and switching times artificially elongated, seems to be a good method for sorting out specimens of inherently poor structure which are prone to volumetric degradation. On the contrary, switching power levels of bipolar IC transistors are so low that the whole bulk-degradation effect can be neglected and so a costly switching-operation life test seems as unreasonable as superfluous at IC-s, at least as compared to effective but cheap d.c. operational methods.     

Transient response of a transistor-tunnel diode hybrid combination with resistive feedback

An approach is suggested for studying the transient behavior of a transistor-tunnel diode hybrid combination with resistive feedback which shows an improved switching speed. The method uses the charge-control model for the transistor and empirical power functions for the tunnel diode. Experimental observations with tunnel diode in combination with slow and gold-doped switching transistors demonstrate that the models used in the analysis are satisfactory for engineering calculations.     

Charge-control modeling of power bipolar junction transistors

This paper describes an improved lumped circuit model of power bipolar junction transistors (BJTs) that can predict the turn-off fall time to a greater accuracy than currently available models. Though the existing models simulate the storage time and delay time to a good accuracy, the fall time performance is neglected. This is because the existing models do not account for the charge decay due to recombination. The model presented in this paper is based on the charge dynamics of the device. The charge dynamics are explained in detail using simulation results from an advanced two-dimensional (2-D) device and circuit simulator. Based on a physical understanding of the charge dynamics, this model is implemented to incorporate the charge decay due to recombination to account for the current tail during turn-off. The lumped-circuit model is implemented in PSPICE using the existing quasisaturation model along with controlled sources. To validate the model, the device was subjected to hard- as well as soft-switching renditions (zero current switching and zero voltage switching). The modeled results are observed to have a good match with measured results     

On the storage time of InGaAs/InP bipolar transistors

The collector storage time was measured for InGaAs/InP bipolar transistors. For the evaluation, the transistors were driven into deep saturation choosing a test condition with no reverse base current. Devices comprising a homojunction- and a modified wide-gap-collector structure, respectively, were compared. For the latter device structure a marked reduction of the storage time by a factor of 10 was found.