高k栅介质小尺寸双栅GeOI MOSFET电特性 模拟及结构优化

The influences of the main structure and physical parameters of the dual-gate GeOl MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium （Ge） channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect （SCE） and drain-induced barrier lowering （DIBL） effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10-18 nm and （5-9）×1017 cm-3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8-1 nm and 15-30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved： on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV.     

Local crystal structural modifications in pulsed laser deposited high-k dielectric thin films on silicon and germanium

The thin film growth conditions are correlated with the local structures formed in Hf_xZr_1−xO₂ (x=0.0–1.0) high-k dielectric thin films on Si and Ge substrates during deposition. Pulsed laser deposition (PLD) technique has been used in the synthesis of the thin films with systematic variations of substrate temperature, Zr content of the targets and substrate selection. The local structural information acquired from extended X-ray absorption spectroscopy (EXAFS) is correlated with the thin film growth conditions. The response of the local structure around Hf and Zr atoms to growth parameters was investigated by EXAFS experiments performed at the National Synchrotron Light Source of Brookhaven National Laboratory. The competing crystal phases of oxides of Hf were identified and the intricate relation between the stabilized phase and the parameters as: the substrate temperature; Hf to Zr ratio; have been revealed. Specifically, HfO₂ thin films on Si(1 0 0) exhibit a tetragonal to monoclinic phase transformation upon increase in the substrate temperature during deposition whereas, HfO₂ PLD films on Ge(1 0 0) substrates remain in tetragonal symmetry regardless of the substrate temperature.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

一种具有高K栅介质与低k侧壁介质的PNPN型隧穿晶体管研究

本文提出了一种具有高K栅介质及低K侧壁介质的PNPN型隧穿场效应晶体管,并通过二维仿真研究了栅电场和侧壁电场对隧穿场效应晶体管性能的影响。结果表明高K栅介质可以增强栅对沟道的控制能力,同时低K侧墙介质有助于增大带带隧穿的几率。具有这种结构的隧穿场效应晶体管器件具有很好的开关特性、大的开态电流以及良好的工艺容差。该器件可以应用于低功耗领域,并有可能作为下一代CMOS技术的替代者之一。     

Thermal stability of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO₂ films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density.     

小尺寸堆栈高k栅介质GaAs nMOSFET阈值电压模型

通过求解沟道的二维泊松方程,建立了小尺寸高k栅介质GaAs MOSFET的阈值电压模型．模型包括了短沟道效应、漏致势垒降低效应和量子效应．模拟结果与TCAD仿真结果符合较好,证实了模型的正确性和实用性．利用该模型,分析了堆栈高k栅介质结构及其物理参数对阈值电压漂移的影响以及阈值电压的温度特性．结果表明,堆栈栅介质结构能有效抑制边缘场和DIBL效应,改善MOSFET的阈值特性和温度特性;未考虑量子效应的模型过高估计了温度对阈值电压的影响。     

Behaviour of injected electrons in high-k dielectric layers

The programming operation in memory device consists of an injection of electrons into the gate dielectric (GD). In many cases, oxide–nitride–oxide (ONO) is used as a GD. A stability of the spatial profile of injected electrons (IE) determines the quality of the memory device. Computer simulations showed that injection of electrons into GD leads to the formation of small charge droplets out of the initial spatial profile of IE. Such a droplet is named as parasitic peak (PP). The simulation of IE redistribution in GD shows that the Coulomb scattering of newly injected carriers on PPs plays an important role in the evolution of the device parameters in conditions of long-term exploitation. The computer model of ONO with high-k layers (HKL) is developed to study the retention parameters of the device in dependence on the type of HKL and on the thickness of GD. The influence of scaling down of the dielectric film with HKL on IE redistribution in GD is investigated. Simulations showed that the possibility of scaling down the thickness of ONO stack with HKL depends not only on the tunnelling effects but also on the multiple scattering processes in ONO with HKL.     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

Structural and interfacial properties of high-k HfOxNy gate dielectric films

The thermal stability and interfacial characteristics for hafnium oxynitride (HfO_xN_y) gate dielectrics formed on Si (1 0 0) by plasma oxidation of sputtered HfN films have been investigated. X-ray diffraction results show that the crystallization temperature of nitrogen-incorporated HfO₂ films increases compared to HfO₂ films. Analyses by X-ray photoelectron spectroscopy confirm the nitrogen incorporation in the as-deposited sample and nitrogen substitution by oxygen in the annealed species. Results of FTIR characterization indicate that the growth of the interfacial SiO₂ layer is suppressed in HfO_xN_y films compared to HfO₂ films annealed in N₂ ambient. The growth mechanism of the interfacial layer is discussed in detail.     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

Silicate formation at the interface of Hf-oxide as a high-k dielectrics and Si(0 0 1) surfaces

The composition and chemical bonding of the first atoms across the interface between Si(0 0 1) and the gate dielectrics determine the quality of gate stacks. An analysis of that hidden interface is a challenge as it requires high sensitivity in both elemental and chemical state information. We used synchrotron radiation (SR) based photoelectron spectroscopy and, in particular, X-ray absorption spectroscopy in total electron yield and total fluorescence yield at the Si2p and the O1s edges to address this issue. We report on results for Hf oxide prepared by ALD and compare to Pr₂O₃/Si(0 0 1). For Hf oxide thin films we find evidence for the silicate formation at the interface as derived from the characteristic features in the X-ray absorption spectra at the Si2p and the O1s edges. Resonant photoelectron spectroscopy is used to analyze the absorption band in detail. Following the resonant profiles of initial and final states we deduce from the resonant behaviour a charge donation via a Si-induced charge transfer.     

ZrAlO ternary oxide as a candidate for high-k dielectrics

ZrAlO thin films were prepared by the pyrosol process. Four different cases were considered taking as basis a solution of 0.025 M zirconium acetylacetonate (ZrAAc) and 5 at% of aluminum acetylacetonate (AlAAc) dissolved in pure methanol. Films of case A, were deposited with the mentioned solution and subjected to rapid thermal annealing (RTA). For case B, a small volume of water was added to start solution. Case C, were similar samples of case B, but with a post-deposition RTA. Case D, were Si/Al₂O₃/ZrAlO/Al stacks with post-deposition RTA, using water in the start solution. XPS profiles show that the relative chemical composition of deposited materials is affected by the volume of water added (Vw). The aluminum concentration in the films acquires values as high as or higher than zirconium concentration for increasing Vw. All the prepared samples were amorphous as indicated by the X-ray diffraction (XRD) spectra, even for large integration times. Current–voltage (I–V) and capacitance measurements were carried out in metal–insulator–metal (MIM) devices (Corning-glass/TCO/ZrAlO/Al) and I–V and simultaneous capacitance–voltage (C–V) measurements were performed in metal–oxide–semiconductor (MOS) devices (Si/ZrAlO/Al and Si/Al₂O₃/ZrAlO/Al). Leakage currents of the order of 10⁻⁴ A/cm², were typically obtained in MIM devices, whereas for some MOS devices, leakage currents of the order of 10⁻⁷ A/cm² were obtained. Dielectric constant (k) values of the order of 24 were calculated for MIM devices and k values ranging from 12.5 up to 17 were calculated for MOS devices.     

Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO₂/HfAlO/SiO₂ triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250 °C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler-Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

超薄EOT高K金属栅结构中串联电阻效应对瞬时击穿特性的影响

本文研究了超薄EOT高K金属栅MOS电容结构的瞬时击穿特性。由于串联电阻效应的影响,MOS电容的瞬时击穿特性的面积依赖关系与理论推导不符。器件中的串联电阻可以通过对IV特性的FN拟合得到。在本文的器件结构中,经验证得到串联电阻主要是由于电极的不对称性引起的扩展电阻。本文提出一种采用串联模型对击穿分布特性进行修正的方法。修正后的瞬时击穿特性与面积的依赖关系符合泊松面积归一规律,这说明对于超薄EOT的高K金属栅结构,瞬时击穿的机制与时变击穿的机制相同,都是由缺陷产生过程导致的击穿过程。