Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

Unified quasi-static MOSFET capacitance model

An accurate calculation of MOSFET capacitance-voltage (C V) characteristics has to account for the bulk charge which is affected by nonuniform doping profiles and short-channel effects. In an approach based on the unified charge control model (UCCM), the voltage dependencies of the bulk charge are related to the standard parameters of the body plots which are routinely measured during MOSFET characterization. The results of the C-V calculations based on this model are in good agreement with experimental data and calculations based on the standard BSIM model. Compared to the BSIM simulations, the present model more accurately describes capacitances related to the bulk charge and the device subthreshold behavior, and it is suitable for incorporation into circuit simulators     

Electrical characterization and modeling of alternating-currentthin-film electroluminescent devices

Electrical characterization of evaporated ZnS:Mn alternating-current thin-film electroluminescent (ACTFEL) devices is accomplished by capacitance-voltage (C-V) analysis. Interpretation of these C-V characteristics is aided by SPICE modeling and by electrical characterization of an ideal ACTFEL device constructed from discrete components, based on a simple equivalent circuit for the ACTFEL device. Various features of the C -V curve are ascribed to equivalent circuit parameters and associated device physics parameters     

The electrical characteristics of bulk unipolar camel diodes inpre-amorphized silicon

Barrier heights derived from the measured forward I-V characteristics are consistent with barrier heights calculated using doping profiles determined by secondary ion mass spectroscopy (SIMS). Reverse-bias I-V characteristics show excessive barrier pull-down, which is explained by the presence of excess donors at the original amorphous-single-crystal interface. The existence of these donors has been confirmed by C-V profiling. A reduction in excess donor density by plasma hydrogenation has led to a corresponding reduction in the reverse-bias barrier pull-down. These camel diodes have reverse-bias characteristics superior to those of diodes fabricated in single-crystal silicon     

A new technique for determining the generation lifetime profile inthin semiconductor films with application to silicon-on-insulator (SOI)substrates

A differential technique which uses reverse-biased current-voltage (I-V) and capacitance-voltage (C-V) measurements on a p-n junction or a Schottky barrier diode for determining the generation lifetime profile in thin semiconductor films is discussed. It is shown that the bias-independent current can be eliminated by this differential technique. Furthermore, any error caused by field-enhanced current can be estimated. This method has been used to determine the generation lifetime profile in thin silicon epitaxial film grown on SIMOX substrates     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)     

On the charge control of the two-dimensional electron gas foranalytic modeling of HEMTs

A simple charge control model is developed for the two-dimensional electron gas (2-DEG) of high-electron-mobility transistors (HEMTs). This model explicitly takes into account the effective distance of the 2-DEG from the heterointerface and has been developed for use in analytic I-V and C-V modeling. In this model, the Fermi energy level versus the 2-DEG sheet carrier-concentration is represented by a simplified expression derived from the triangular potential well approximation and is shown to be dominated by terms with different functional forms in two distinct operation regions: a moderate carrier-concentration region and a subthreshold region. The validity of the analytic charge control model is supported by the calculated results of a self-consistent quantum mechanical model     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Low-temperature mobility measurements on CMOS devices

The surface channel mobility of carriers in n- and p-MOS transistors fabricated in a CMOS process was accurately determined at low temperatures down to 5 K. The mobility was obtained by an accurate measurement of the inversion charge density using a split C-V technique and the conductance at low drain voltages. The split C-V technique was validated at all temperatures using a one-dimensional Poisson solver (MOSCAP) which was modified for low-temperature application. The mobility dependence on the perpendicular electric field for different substrate bias values appeared to have different temperature dependences for n- and p-channel devices. The electron mobility increased with a decrease in temperature at all gate voltages. On the other hand, the hole mobility exhibited a different temperature behavior depending upon whether the gate voltage corresponded to strong inversion or was near threshold     

Modeling and experimental results for C(V) in anabrupt isotype n Al0.5Ga0.5As/GaAs heterojunction

The differential capacitance C of an abrupt isotype n Al_0.5 Ga_0.5As/GaAs heterojunction has been modeled by directly calculating the dependence of the space charge on the voltage V at its terminals. The electron charge distribution was calculated considering the 2-D electron gas by simultaneously solving the Schrodinger and the Poisson equations, DX centers included. Results from this model predict an asymmetric bell-shape dependence of C on V, with a maximum near the contact potential, and are in good agreement with experiment. This further provides experimental evidence of Γ-Γ and X-X valley coupling for electrons traveling across the heterojunction. For voltage values not too close to the contact potential, it was possible to find a simple method, based on a total depletion, that gives a good fit to experiment     

Effect of dopant redistribution, segregation, and carrier trappingin As-implanted MOS gates

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi₂ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi₂. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

A new technique to determine the average low-field electronmobility in MESFET using C-V measurement

A method to determine the average low-field mobility using the number of electrons available for the conduction based on C-V measurement is proposed. This technique requires neither information of the doping profile in the channel, nor the exact value of the threshold voltage. For a D-mode MESFET, the average electron mobility magnitude is compared with that of the C. Chen and D.K. Arch (1989) method. The technique to determine the average electron mobility in the channel described is much simpler. Based on C- V measurement, good agreement is obtained between experimental data and simulation calculation for the electron density in the channel. Using the proposed method, the dependence of average electron mobility on the gate voltage is also proposed. Using the proposed method for determining the average electron mobility, the effect of a p-buried layer on the mobility was investigated, and is in good agreement with the physical phenomena     

A new method for fixed oxide charge determination using a dual-gateMOS capacitor

A new method for fixed oxide charge determination at the silicon-silicon-dioxide interface is presented. It is based on high-frequency C-V measurements of a dual-gate MOS capacitor. Using this technique the fixed oxide charge can be accurately without knowledge of the work-function difference by means of one simple measurement. Due to its simplicity and ease of automation it can be applied to characterization and process optimization of MOS technology     

Magnetotransconductance profiling of mobility and doping in GaAsMESFETs

Electron mobility profiles of GaAs MESFETs have been measured using the magnetotransconductance technique and corrected using in situ measurements of parasitic resistances. It is shown that with this technique both mobility and carrier density profiles versus depth can be calculated without C-V data. This enables complete mobility and carrier density profiles to be obtained on short-gate-length packaged devices without the inherent difficulties of the C-V method and its attendant inaccuracies near the active layer-substrate interface. The results for two commercial packaged devices at room temperature, which indicate mobilities of 3500 to 4500 cm²/V/s and peak carrier concentrations of 1.2 to 2.0×10¹⁷ cm^-3, are given     

Frequency-dependent capacitance-voltage characteristics foramorphous silicon-based metal-insulator-semiconductor structures

A frequency-dependent capacitance-voltage model for the a-Si:H-based MIS structure is presented along with an alternative direct measurement method. The static C-V model is derived based on the static I-V model developed using the simplified CFO band model for the a-Si bulk bandgap states and the simplified Davis-Mott model for the surface states. The frequency variation of the measured capacitance, using a somewhat modified TFT, is modeled with the lateral flow transmission line model. These models can be used to monitor TFT-fabrication parameters and to extract accurate capacitance model parameters of TFTs     

Light-to-input nonlinearities in an R-LED series network

The light-to-current (L-I) and light-to-voltage (L-V) differential nonlinearities in the simple network of a customary LED and an external resistor R in series are analyzed and calculated theoretically and compared with experimental data. Particular emphasis is placed on the influence of the log-arithmetic slope ν of the L-I characteristic and the bias current I upon the ratio of the corresponding nonlinearity parameters. It is thus deduced that, for a given optical power P, over superlinear portions of the L-I curve (ν>1) the L-I linearity is typically better than its corresponding L-V linearity. On the contrary, when the L-I dependence is sublinear (ν<1) the voltage driving scheme may ensure for the R-LED network, or the LED alone, a local L-V response much more linear than the L-I response, provided that appropriate (optimum) I and/or R values are chosen     

A technique for profiling the epilayer channel of surface acousticwave devices on piezoelectric semiconductors

A method for determining the impurity doping profile of the transport epitaxial layer channel of surface acoustic wave (SAW) devices on piezoelectric semiconductors is presented. This technique utilizes the same structure already present in these devices; thus, testing can be done without altering or damaging the device. Another advantage of this technique over the equivalent C-V measurement is the high sensitivity of the transverse acoustoelectric voltage (TAV) to higher resistivity materials. Experiments and estimated doping profiles are presented along with the theoretical analysis of the measurement