PCI Express总线事务层IP核设计及实现

介绍了第三代输入输出总线PCI Express的事务层组成结构与功能,自顶向下对事务层进行了系统级设计,运用硬件描述语言Verilog HDL对其实现.使用Synopsys VCS进行功能仿真,得出了仿真波形,验证了该设计的正确性,符合PCI Express事务层协议.     

基于PROTEUS的单片机温度采集系统设计与仿真

本文介绍一种基于Proteus 仿真实现的数字温度采集系统,阐述了系统的工作原理、硬件电路以及软件设计。该系统吸收了硬件软件化的思想,大部分功能通过软件来实现,硬件电路设计简单明了,稳定性大大提高。利用先进的嵌入式仿真平台Proteus进行系统软硬件协同仿真,以检验和评估设计的可行性和稳定性。仿真结果表明,Proteus在嵌入式开发领域具有方便快捷、降低设计成本、提高工作效率等优点。     

基于PROTEUS的单片机温度采集系统设计与仿真

本文介绍一种基于Proteus仿真实现的数字温度采集系统,阐述了系统的工作原理、硬件电路以及软件设计。该系统吸收了硬件软件化的思想,大部分功能通过软件来实现,硬件电路设计简单明了,稳定性大大提高。利用先进的嵌入式仿真平台Proteus进行系统软硬件协同仿真,以检验和评估设计的可行性和稳定性。仿真结果表明,Proteus在嵌入式开发领域具有方便快捷、降低设计成本、提高工作效率等优点。     

一种软硬件协同设计工具原型及其设计描述方法

软硬件协同设计工具不但需具有软硬件功能划分的能力,而且应可实现系统级设计到软硬件基本结构的综合。提出一种利用进程代数为高层设计语义基础,可重用现有软硬件设计工具资源的软硬件协同设计工具的实现方案框架,重点讨论其中的设计描述问题。采用这种基于语言变换的软硬件协同设计工具方案有利于对系统的活性、安全性、接口一致性等性质进行高层仿真与形式验证,具有可用性、易扩展好等优点。     

对SoC芯片全面验证的仿真结构的研究

研究构成仿真环境的策略及软硬件协同验证环境的接口实现,介绍了用于功能和性能验证的软件伪随机测试生成方法.该方法对SoC和复杂的板机系统进行可测性设计的优化验证,大大降低测试成本,缩短了系统开发周期.     

一种32 Bit SoC软硬件协同验证环境的实现

软硬件协同验证是系统芯片设计的重要组成部分。针对基于32 Bit CPU核的某控制系统芯片的具体要求,提出了一种系统芯片软硬件协同验证策略,构建了一个软硬件协同验证环境。该环境利用处理器内核模型支持内核指令集的特性运行功能测试程序,实现SoC软硬件的同步调试,并能够快速定位软硬件的仿真错误点,有效提高了仿真效率。该SoC软硬件协同验证环境完成了设计目的,并对其他系统芯片设计具有一定的参考价值。     

基于SPARC V8的事务级SoC验证平台设计

针对片上系统SoC架构设计和嵌入式软件开发的需求,采用事务级建模方法使用SystemC完成了基于SPARC V8的事务级SoC验证平台的设计.为降低设计复杂度和提高仿真速度,基于解释-执行技术完成SPARC V8处理器指令精确事务级模型建模,并利用SystemC中的分层通道机制完成AMAB总线、中断控制器、UART、定时器等设备的事务级建模.完成事务级SoC验证平台的构建后,使用测试基准程序组Mibench对该验证平台的功能和仿真速度进行了验证.仿真结果证明了其功能正确,并且仿真速度相对于RTL SoC验证平台有大幅度的提高.     

基于FPGA的ⅡR数字滤波器协同仿真

文章引入FPGA来实现数字滤波器,在对一个4阶级联型ⅡR滤波器的系统仿真中,采用了两种仿真方法。与传统仿真方法相比,协同仿真打破了软硬件间的屏障,大大加快了系统的功能验证。实验结果表明：该验证方法具有结果直观,操作简单,效率高等优点。     

基于工控软件的仿真培训系统开发与研究

介绍了某化工厂工艺全流程仿真培训系统的开发过程。该系统运用PC机网络形式,模拟了化工生产的动态过程和仿真TDC3000型DCS系统,同时具备现场模拟功能以及教师控制功能,能够通过该系统对现场工艺操作员、组态工程师和仪表技术工人进行培训,以提高工作人员的理论水平和实际操作技能。文中将从该仿真培训系统的总体结构、软硬件设计、系统特点和功能等方面介绍该系统的设计与实现。     

雷达结构系统协同仿真环境

针对雷达研制过程中结构系统涉及到的刚强度、散热、流场模拟、模态、振动特性、疲劳寿命等仿真问题及其现状,提出了应用协同仿真技术来进行现有的仿真工具软件、数据、流程和人员整合,搭建一套协同的虚拟产品开发环境,并阐述了该协同仿真环境的内涵和详细功能需求.结合目前的技术水平,指出了该协同仿真环境应具备的基本功能,提出了可行的实施思路,给出了某典型产品的协同仿真流程,最后提出了通过协同仿真环境对仿真模型进行成熟度管理办法,实现仿真经验积累.     

Reliability Properties Assessment at System Level: A Co-Design Framework

This paper introduces an enhanced hardware/software co-design framework allowing the designer to introduce hardware fault detection properties in the system under consideration. By considering reliability requirements at system level, within a hw/sw co-design flow, it is possible to evaluate overheads and benefits of different solutions. System specification, hardware and software concurrent fault detection design methodologies and hw/sw partitioning are the three key factors taken into account. The paper discusses these aspects providing a complete overview of the reliability co-design project.     

Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures

The purpose of this paper is to present a novel methodology for assessing the quality of architecture solutions of hw/sw systems, with particular emphasis on testability. Criteria and metrics for quality assessment are proposed and used to assist the design team in selecting a best-fitted architecture that satisfies not only functional requirements, but also test requirements. The methodology makes use of object-oriented modeling techniques. Near-optimum clustering of methods and attributes into objects is carried out, in such a way that objects with moderate complexity, low coupling and high functional autonomy, result. The main features of the methodology are ascertained through a case study.     

基于System C的多处理器片上系统软硬件协同仿真

给出了基于SystemC的处理器片上系统(System On a Chip)的协同仿真的两种方法.并通过对系统的仿真,对两个方法进行了对比,给出了在仿真间隔时间、速度和其他性能之间的比较.对目前SOC的软硬件协同设计验证有一定的实际意义.     

A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse.     

FPGA implementation of high-speed neural network for power amplifier behavioral modeling

In this paper, a high-speed pipelined architecture of dynamic neural network is proposed for power amplifier behavioral modeling. This architecture is implemented on field programmable gate array (FPGA) using Xilinx system generator and Virtex-6 FPGA ML605 Evaluation Kit. The novelty of the proposed architecture is that it provides higher operating frequency, lower output latency, and less required resources. These improvements are obtained by reducing the bit-width data and by efficiently redistributing the inserted pipelining delays. The new pipelined architecture is evaluated and compared to the conventional and pseudo-conventional ones in terms of the resource utilization, the maximum operating frequency, and the modeling performances using the 16-QAM modeled test signal. This architecture is verified using JTAG hardware co-simulation both for single step and free-running clock modes.     

Automated software attack recovery using rollback and huddle

While research into building robust and survivable networks has steadily intensified in recent years, similar efforts at the application level and below have focused primarily on attack discovery, ignoring the larger issue of how to gracefully recover from an intrusion at that level. Our work attempts to bridge this inherent gap between theory and practice through the introduction of a new architectural technique, which we call rollback and huddle. Inspired by concepts made popular in the world of software debug, we propose the inclusion of extra on-chip hardware for the efficient storage and tracing of execution contexts. Upon the detection of some software protection violation, the application is restarted at the last known safe checkpoint (the rollback part). During this deterministic replay, an additional hw/sw module is then loaded that can increase the level of system monitoring, log more detailed information about any future attack source, and potentially institute a live patch of the vulnerable part of the software executable (the huddle part). Our experimental results show that this approach could have a practical impact on modern computing system architectures, by allowing for the inclusion of low-overhead software security features while at the same time incorporating an ability to gracefully recover from attack.     

一种基于ARM7TDMI的用户可重构SoC构架研究

提出了一种基于ARM7TDMI嵌入式内核用户可重构系统芯片构架.该架构由ARM系统的固定逻辑、重构控制模块、数据总线接口控制模块组成,相对于专用系统芯片或FPGA,该架构表现出很大的突出的灵活性、高效性.最后还对用户可重构芯片的集成开发环境及联合仿真等方面进行了详细的论述.     

车载逆变电源的Saber与Simulink联合仿真

在此运用软件Saber和Matlab／Simulink对车栽逆变电源系统进行了联合仿真,得到具有闭环控制功能的车载逆变电源系统的实时仿真结果。通过仿真结果表明利用Saber和Matlab／Simulink软件的联合仿真,可以实现精确的器件模型,搭建控制系统更方便,保证了系统仿真的收敛性,简化了系统仿真的难度,缩短了仿真时间。     

基于Jenkins的持续集成系统研究

本文基于大规模软件产品研制背景,分析了软件开发面临的诸多问题,研究了在项目开发过程中引入持续集成的必要性,并对持续集成系统进行整体设计。本文将整个持续集成过程划分为版本控制、自动化构建以及自动化测试三个核心环节,对这三大核心模块进行详细设计,实现了一套基于Jenkins工具的持续集成系统。其中版本控制模块采用了支持分布式工作流的SVN代码存储库,自动化构建模块主要完成Jenkins持续集成服务器的搭建及配置,自动化测试模块主要实现了一套基于库博国产化工具的自动化测试框架。本文设计并实现的持续集成系统利用自动化的技术手段,在实际案例的应用中实现了从代码提交、到代码编译、单元和集成测试以及测试结果反馈的一系列过程。