Self-assembling MEMS variable and fixed RF inductors

Inductors play a key role in wireless front-end circuitry, yet are not generally well suited for conventional RF integrated-circuit (RFIC) fabrication processes. We have developed inductors that can be fabricated on a conventional RFIC silicon substrate, which use warping members to assemble themselves away from the substrate to improve quality factor (Q) and self-resonance frequency (SRF), and to provide a degree of variation in inductance value. These self-assembling variable inductors are realized through foundry provided microelectromechanical systems (MEMS) processing and have demonstrated temperature stable Q values greater than 13, SRF values well above 15 GHz, and inductance variations greater than 18%. Simulations suggest the potential for Q values above 20 and inductance variations greater than 30%, with optimized processing     

红外探测器倒装互连技术进展

随着红外焦平面技术的发展,红外探测器探测波段已由单波段变为双色及四色波段,半导体元件的封装数量由最初的数十个发展到数百万个,I/O输出密度不断增大,传统微互联技术如引线键合技术、载带自动焊技术等已根本无法满足器件要求。倒装焊技术以其封装尺寸小、互联密度高、生产成本低的特点越来越受到人们的亲睐。倒装互连工艺主要包括:UBM 制备、铟膜沉积、回流成球、倒压焊、填充背底胶。介绍了各工艺步骤的发展状况,并对铟膜沉积、铟柱增高工艺进行详细阐述。     

倒装芯片市场竞风流

倒装芯片技术受到两大推力而走向广泛应用,一是受微处理器ASICKE及高端ＤＳＰ器件高性能需求所推动;一是受籽芯(ｄｉｅ)尺寸,小封装成本的推动。高性能需求所推动向中等引脚数量的发展预示着这一技术应用的加速,至于设备的改进和产业的成熟,乃是表示未来成本要下降。     

Flip chip underfill flow characteristics and prediction

This paper presents recent results on underfill flow characterization. The flow properties of a number of commercial and experimental underfills were recorded and analyzed using quartz test chips with specially designed bump patterns (e.g., peripheral, full array, and mixed designs). Each was bonded onto an organic laminate substrate to form a flip chip package. Underfill was then applied to the packages and flow time, filler settling, and air entrapment were evaluated. Good flow can be described in terms of three measurable parameters, namely, viscosity, contact angle, and more importantly, filler size and distribution. Viscosity and contact angle are commonly used in Hele Shaw and Washburn models. However, these models do not take filler properties into consideration. In general, underfills with particles less than 5 μm exhibited faster and more uniform flow fronts than materials with larger particles. The best flowing materials worked well with standoff heights between 50 and 75 μm, while the poorer flowing materials showed streaking, voiding, and fingering at these heights. At gaps of 25 μm, however, nearly all the materials exhibited pronounced and reproducible streaking     

A low-power low-phase-noise LC VCO with MEMS Cu inductors

A 2-3 GHz CMOS inductance-capacitance (LC) voltage-controlled oscillator (VCO) integrated with high-Q micro-electromechanical systems (MEMS) Cu inductors is reported. While dissipating only 6.3 mW, a phase noise of -121 dBc/Hz at 600 kHz offset from 2.78 GHz carrier is achieved. This MEMS VCO has the largest power-frequency normalized figure-of-merit (12.5 dB) among the Si bipolar and CMOS LC VCOs.     

RF VCO tuning using MEMS piezoelectric actuated variable inductors

This paper presents a study on the use of microsystems technology in the design of radio frequency voltage-controlled oscillators. In particular, the application of a micro-electro-mechanical systems (MEMS) based variable inductor for frequency tuning purposes is presented. Although traditionally a MEMS variable inductor is considered as a means to extend the tuning range, in this work it is shown that with correct inductor design it is also possible to facilitate and improve the voltage-controlled oscillator design in terms of phase noise response and power consumption in comparison to a design based on standard capacitive tuning.     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件-智能像素面阵,对倒装焊的工艺过程作了简要的介绍.该面阵采用铟做凸点材料,制作了输入输出数达64×64的凸点电极阵列,并采用回流焊的方式,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接,形成输入输出引线间距只有80μm的面阵器件.     

Flip chip die attach development for multichip mechatronics powerpackages

New package innovations are needed to address the next generation system requirements of the automotive market. Enhanced system functionality from semiconductor components and overall cost reduction demands drive multichip package solutions. The use of semiconductor devices to switch, control and monitor high current loads will integrate logic and power devices on a common substrate with requirements for effective power dissipation, current carrying capability and fine width conductor features for the control device and interconnections. To achieve these goals Motorola's Advanced Interconnection Systems Laboratory, Munich, has developed a new package concept, a multichip mechatronics power package, utilizing flip chip die attach technology and electroplated eutectic SnPb solder bumps. With the goal to deliver an advanced package platform to cover different power levels in the system architecture,the several substrate technologies were evaluated     

芯片封装互连新工艺热超声倒装焊的发展现状

介绍了一种芯片封装互连新工艺热超声倒装芯片连接工艺.在比较当前多种芯片封装方式的基础上,总结了这一工艺的特点及优越性,并详细论述了当前这一工艺的技术进展与理论研究状况,指出该工艺是芯片封装领域中具有发展潜力的新工艺.     

Failure mode analysis of MEMS suspended inductors under mechanical shock

Micro-electromechanical system (MEMS) suspended inductors have been widely studied in recent decades because of their excellent radio frequency performance. However, few studies have been performed on the failure analysis of MEMS suspended inductors under mechanical shock. In this study, the failure of MEMS suspended inductors with a planar spiral coil is investigated through analytical and experimental methods. We present a stress and deformation analysis to study the failure mode of the suspended inductors under shock. To verify the theoretical analysis, MEMS inductors are designed and fabricated, and shock tests are carried out. The shock tests show that the failure mode of the MEMS suspended inductors is a fracture that occurs at the ends of the inductor coil, and the test results agree with the theoretical analysis.     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件—智能像素面阵 ,对倒装焊的工艺过程作了简要的介绍。该面阵采用铟做凸点材料 ,制作了输入输出数达 6 4× 6 4的凸点电极阵列 ,并采用回流焊的方式 ,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接 ,形成输入输出引线间距只有 80 μm的面阵器件     

水基流延成型制备片式电感器件研究

以聚丙烯酸铵为粉体分散剂,聚乙烯醇和丙烯酸乳液为复合粘结剂,聚乙二醇(PEG600)为增塑剂,制备了Ni-Zn水基流延成型铁氧体浆料。研究了Ni-Zn铁氧体粉体在水中的稳定性,以及粘结剂含量、固相含量对浆料性能、流延薄带性能及薄带压合性能的影响。结果表明:在pH=9.5、分散剂含量(质量分数)为6‰时,Ni-Zn铁氧体粉体在水中具有较好的稳定性;在聚乙烯醇、丙烯酸树脂和固相含量(质量分数)分别达到6.5%、15%和54.5%时,所制Ni-Zn浆料具有较好的流动性,以其制成的20μm薄带则结构致密、附着力及压合较好、无分层;以水性浆料和有机浆料分别制成的1005型号电感(介质膜厚和线圈匝数相同)在100 MHz下测得的阻抗几乎相同,而前者成本却降低了80%左右。     

Flip chip attachment on flexible LCP substrate using an ACF

In this study the reliability of a flip chip bonding process using anisotropic conductive adhesives (ACA) was evaluated. The flexible substrates used were made of liquid crystal polymer (LCP), which is an interesting new material having excellent properties for flexible printed circuit boards. The test samples were prepared using two different anisotropic conductive films (ACF) having the same fast-cure resin matrix, but different conductive particles. The reliability of the test samples was studied by accelerated environmental tests. In the constant humidity test the temperature was 85 °C and the relative humidity was 85%. The temperature cycling test was carried out between temperatures of −40 °C and 85 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between the behaviour of the conductive particles was seen in the test. While the adhesive having polymer particles had only one failure during testing, the adhesive having nickel particles had a considerable number of failures in both tests. Cross sections of the samples were made to analyze the failure mechanisms.     

印制板上形成凸块的倒芯片安装技术

该文概述了在印制板(PWB)上形成倒芯片安装用的凸块的方法和工艺条件,并进行可靠性试验和评价,确认了Boss B~2it 技术可以实现低成本倒芯片安装。     

Low temperature brazing of chip inductors by abnormal glow discharge plasma

A novel method, by which Cu was deposited on ferrite ceramics with arc-added glow discharge as a precursory procedure and then brazing the ferrite ceramics with vacuum glow discharge, was investigated. This new method can effectively suppress interfacial diffusion and brazing joint oxidation as well as maintain good adhesion in the joint due to low deposition and brazing temperature, the vacuum atmosphere effect, and the cathode sputter-cleaning action of the abnormal glow discharge plasma. The influence of the brazing process parameters on electrical and magnetic properties of the chip inductors is discussed. The optimal deposition and brazing process parameters are presented. Scanning electron microscope line scanning confirms the brazing electrode joints and detected the interfacial diffusion between the joints and the ferrite ceramics.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Flip chip solder joint reliability analysis using viscoplastic and elastic-plastic-creep constitutive models

Both elastic-plastic-creep and viscoplastic constitutive models may be used for inelastic deformation analysis of solder joints. In this paper, a phenomenological approach using elastic-plastic-creep analysis and an Anand viscoplastic model is reported for solder joint reliability. Flip chip soldered assemblies with 63Sn-37Pb solder joints were subjected to a thermal cyclic loading condition of -40 to +125/spl deg/C to assess the solder joint fatigue performance. In the finite-element modeling, the viscoplastic strain energy density per cycle obtained from the viscoplastic analysis is compared with the inelastic (plastic and creep) strain energy density per cycle calculated from the elastic-plastic-creep analysis. The inelastic (plastic+creep and viscoplastic) strain energy density extracted from the finite-element analysis results, at the critical solder joint location, were used as a failure parameter for solder fatigue models employed. It was found that the predicted solder joint fatigue life has a better correlation to the first failure or first-time-to-failure result.     

Flip chip on board: assessment of reliability in cellular phone application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.     

宇航用PB型叠层片式电感器评估试验及应用建议

为验证大电流(PB)型叠层片式电感器(MLCI)应用在宇航工程中的可靠性水平及性能参数冗余量,对PB型MLCI进行了热应力、机械应力、电应力及强化寿命等评估试验,从而掌握了产品在不同应用条件下性能参数的边界余量和极限耐受能力等试验数据。对评估试验结果进行了分析,得出了电参数所呈现变化趋势的具体原因。此外,基于评估试验结果的分析,给出了产品在设计应用时的注意事项和使用指南。     

RF inductors and capacitors integrated on silicon chip by CMOS compatible Cu interconnect technology

High-Q inductors and high-density capacitors have been designed and fabricated with a post-process of additional metal layers on the top of interconnect layers. The fabrication was carried out with advanced Cu interconnect technology, which was compatible with nowadays CMOS backend of line. The Q_max of inductors with inductance from 0.4 to 11 nH was over 11 on low-resistivity silicon substrates. Two kinds of structures of on-chip capacitors, MIM and MIMIM, have been studied. A capacitance of 1.75 fF/μm² has been achieved with MIMIM structure using Si₃N₄ as dielectric.