Effect of forward and reverse substrate biasing on low-frequencynoise in silicon PMOSFETs

Forward body biasing improves the low-frequency noise performance of p-channel metal-oxide semiconductor (PMOS) transistors by about 8 dB/V. Therefore, for analog design, forward body biasing may be preferred if noise is a concern. This is in agreement with the improvement of other MOSFET parameters such as the decrease of the threshold voltage (V_T) or the increase of unity current-gain frequency (f_T) on forward substrate- (or body)-source biasing (V_BS). Also, forward V_BS is very attractive for low voltage supply (V_DD<0.6 V) and low-power, low-noise circuits. A detailed analysis of the dependence of the noise level on VBS and on the gate-source (V_GS) biasing showed that the dependence on V_BS seems to be smaller in weak inversion, and it increases in strong inversion. The dependence on V_GS has a turning point at V_GS≈0.8 V, independent of body bias, which it seems is due to the activation of oxide traps, as the noise waveform showed a random telegraph signal (RTS) component at V_GS >0.8 V. Generally, it is confirmed that the spectral density S _I of the total low-frequency noise of the drain current I_D is proportional to the square of I_D, i.e., S _I∝I_D², but it cannot be clearly ascribed to either number fluctuation or mobility fluctuation models. In addition, both models cannot accurately describe the dependence of the noise level on the body bias     

Dynamic-stress-induced enhanced degradation of 1/f noise inn-MOSFETs

AC-stress-induced degradation of 1/f noise is investigated for n-MOSFETs with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under AC stress is far more serious than that under DC stress. For an ac stress of V_G=0~0.5 V_D, generations of both interface states (ΔD_it) and neutral electron traps (ΔN_et) are responsible for the increase of 1/f noise, with the former being dominant. For another AC stress of V _G=0~V_D. a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔN_et and generation of another specie of electron traps, plus a small amount of ΔD_it. Moreover, under the two types of AC stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation     

On/off current ratio in P-channel poly-Si MOSFETs: dependence onhot-carrier stress conditions

Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V_GS=V_DS=-11 V, but can be increased by a factor of 50 for a stress bias of V_GS=-2 V, V_DS=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V_GS. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation     

Extrinsic base optimization for high-performance RF SiGeheterojunction bipolar transistors

A comprehensive study on the effect of extrinsic base optimization on the RF performance of an advanced SiGe HBT is presented. An optimized extrinsic poly base with its interface to the epi-base passivated by boron ions is demonstrated to enhance the f_max and the current gain almost two times and to reduce the low-frequency 1/f noise ten times and noise figure (NF) 0.5 dB, achieving f_max of 45 GHz, 1/f noise corner frequency of 700 Hz at I_B=1.0 μA, NF⩽1.0 dB at 900 MHz. Early voltage V_A of ⩾200 V is achieved, while maintaining a BV_CEO of ⩾8.0 V     

High-speed InGaP/GaAs transistors with a sidewall base contactstructure

We have fabricated InGaP/GaAs double heterojunction bipolar transistors with a sidewall base contact structure. These transistors operate in both emitter-up and emitter-down modes. Symmetric characteristics of the cutoff frequency f_T=68 GHz and the maximum oscillation frequency f_max=31 GHz were obtained at a base-collector bias V_BC of 0 V. For emitter-down operation, f _T was found to reach a maximum of 78 GHz when the base-collector junction was forward biased at 0.9 V. The product of f _T for emitter-down operation and f_T for emitter-up operation was 5.3×10³ GHz², which is about six times that of previously reported SiGe heterojunction bipolar transistors     

Characterization of flicker noise in GaN-based MODFET's at lowdrain bias

We report systematic characterizations of flicker noise in GaN based MODFET's. The devices were fabricated by MBE on (0001) basal plane sapphire substrates with an 800 Å AlN buffer layer grown at 800°C. Flicker noise was measured across the channel of the devices from room temperature to about 130 K. The voltage noise power spectra, S _V(f), were found to be proportional to 1/f^γ. The frequency exponent, γ, of S_V(f) exhibits systematic dependencies on the device temperature as well as the gate bias, V_G . The variation of the noise power spectra as a function of the drain voltage, V_D, and the gate bias, V_G, were studied in detail and were found to vary as V_D²/(V _G-V_T)^β where β changes with temperature from about 2.1 at room temperature to about 0.9 at 130 K. Analyses of the data show that the noise originated from the thermal activation of carriers to the localized states at the AlGaN/GaN heterointerface in the channel area. The data suggested that the trapping and detrapping of carriers did not lead to fluctuations in the carrier concentration as postulated in the McWhorter's model. However, more work is needed to determine if surface mobility fluctuations played a key role in the 1/f noise     

1/f noise and material defects in HgCdTe diodes

1/f noise is measured on long wavelength diodes as a function of device geometry, band gap, temperature, diode bias, and anneal temperature for a Te-rich CdTe passivation layer. The results show that for these diodes the 1/f noise is a bulk phenomena due to the modulation of generation recombination current associated with defects formed by the interdiffusion of Te-rich CdTe, and that these defects are located in the junction region. No 1/f noise is observed for the lowest interdiffusion anneal temperature.     

1/f noise reduction in PMOSFETs by an additional preoxidationcleaning with an ammonia hydrogen peroxide mixture

1/f noise magnitude in a 15 μm×0.5 μm PMOSFET was remarkably reduced by simply adding a cleaning step using an ammonia hydrogen peroxide mixture (APM) prior to gate oxidation. Gate input-referred noise level for APM-finished PMOSFETs at f=10 Hz was around -128 dBV²/Hz whereas for standard, HF-finished devices, the level was around -114 dBV²/Hz. Flat-band voltages (V_FBs) determined by a capacitance-voltage (C-V) measurement were -0.19 V for an APM-finished PMOS and -0.34 V for a HF-finished PMOS. Based on the V_FB values, interface state densities were determined to be N_it=3.02×10¹¹ cm^-2 for APM-finished PMOS and N_it=6.47×10¹¹ cm^-2 for HF-finished PMOS. Lower interface state density obtained by the APM preoxidation cleaning is consistent with the remarkable reduction in the 1/f noise magnitude     

A new model for the low-frequency noise and the noise levelvariation in polysilicon emitter BJTs

Presents a new, physically-based model for the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs). Evidence of the low-frequency noise originating mainly from a superposition of generation-recombination (g-r) centers is presented. Measurements of the equivalent input noise spectral density (SIB) showed that for BJTs with large emitter areas (AE) S(I_B) is proportional to 1/f, as expected. In contrast, the noise spectrum for BJTs with submicron A_E showed a strong variation from a 1/f-dependence, due to the presence of several g-r centers. However, the average spectrum 〈S(I_B)〉 has a frequency dependence proportional to 1/f for BJTs with large as well as small A_E. The proposed model, based only on superposition of g-r centers, can predict the frequency-, current-, area-, and variation-dependency of 〈S(I_B)〉 with excellent agreement to the measured results     

Physical interpretation of the noise reduction for the generation—Recombination current due to SRH centers in the space-charge layer

The expressions for the noise in the generation-recombination current due to SRH centers in the space-charge layer of junction devices have been recast in a simple form. For low forward bias the noise reduction (Γ²≈ 0.75) is shown to stem from the two-step recombination process, while the high-frequency reduction Γ²≳ 0.5 stems from the noncorrelation of electron and hole transport.     

Novel Hg<Subscript>x</Subscript>Cd<Subscript>1−x</Subscript>Te device structure for higher operating temperature detectors

A novel detector structure in which photons are absorbed in narrow-gap material, but the junction lies in wider bandgap material, has been examined. A possible reduction in bulk 1/f noise by a factor of 33 for a 240 K operation was predicted, based on studies that have suggested that the source of 1/f noise is the p-n junction and the large reduction in 1/f noise, which is observed in conventional detectors when the bandgap is increased. The increased bandgap at the junction produces a potential barrier; however, calculations are presented showing that for T > 150 K the thermal energy of the electrons enables them to cross the barrier and reach the p-n junction before recombining in the active region, thus giving high quantum efficiency. Experiments performed on the diodes showed that the quantum efficiency was maintained as expected, but the 1/f noise was not reduced, suggesting that it does not originate at the p-n junction. However, the structure does give excellent reverse-bias characteristics with low breakdown even at 2-V reverse bias.     

High detectivity InGaN-GaN multiquantum well p-n junction photodiodes

InGaN-GaN multiquantum well (MQW) p-n junction photodiodes with semi-transparent Ni-Au electrodes were fabricated and characterized. It was found that the fabricated InGaN-GaN p-n junction photodiodes exhibit a 20-V breakdown voltage and a photocurrent to dark current contrast ratio of /spl sim/10/sup 5/ when a 0.4-V reverse bias was applied. The peak responsivity at 380 nm was 1.28 and 1.76 A/W with a 0.1- and 3-V applied reverse bias, respectively. Furthermore, an internal gain was found from our InGaN-GaN MQW p-n junction photodiodes possibly due to the long-lifetime of GaN based materials. Also, it was found that the low frequency noise of our photodiodes was dominated by the 1/f type noise. For a given bandwidth of 500 Hz, the corresponding noise equivalent power and normalized detectivity D/sup */ were found to be 6.34/spl times/10/sup -13/ W and 4.45/spl times/10/sup 11/ cm/spl middot/Hz/sup 0.5/ W/sup -1/, respectively.     

A BSIM3-based flat-band voltage perturbation model for RTS and 1/fnoise

Recently, a new random telegraph signal (RTS) noise model for the drain current fluctuations (ΔI_d) associated with single-carrier trapping and detrapping has been developed from a flat-hand voltage perturbation (ΔV_fb) of the BSIM3 current-voltage (I-V) model (Martin et al., 1997). The model's accuracy in predicting the gate bias and geometry dependence of RTS magnitudes has been verified and summarized. In this letter, the perturbation model has been extended to yield a new formulation for the scattering coefficient (α) which predicts the magnitude and bias dependence of 1/f noise without fitting parameters. The absence of fitting parameters allows for a direct determination of the oxide trap density (N_t(E_fn)) from 1/f noise measurements. Results suggest that the BSIM3-based model accurately predicts the bias and geometry dependence of 1/f noise, that N₂O annealing may significantly increase the oxide trap density at strong inversion and that the bias dependence of N_t(E_fn) contains most of the 1/f noise dependence upon V_g     

A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltageCMOS with forward bias

In a speed-adaptive threshold-voltage CMOS (SA-V_t CMOS) scheme, the substrate bias is controlled so that delay in a circuit remains constant. The substrate bias is continuously changed from -1.5 V of reverse bias to 0.5 V of forward bias in order to compensate for fabrication-process fluctuation, supply-voltage variation, and operating-temperature variation. Advantages and disadvantages of substrate bias control with the forward bias are discussed. The SA-Vt CMOS scheme with forward bias is implemented in a 4.3M-transistor microprocessor. The controller occupies 320×400 μm in area and consumes 4-mA current. A 0.5-V forward bias raises the maximum operating frequency of the processor by 10%. The processor provides 400 VAX MIPS at 1.5-1.8 V supply with 320-380-mW power dissipation, that is, it achieves 1.2-GIPS/W performance     

On the geometry dependence of the 1/f noise in CMOS compatiblejunction diodes

This paper examines in detail the low-frequency (LF) noise behavior of Si n⁺p junction diodes in forward operation. Diodes fabricated on various types of Si substrates (FZ, epitaxial, and Cz) and with different geometries are studied in the current range 0.1-250 μA in order to investigate the impact of these parameters. It is demonstrated that different kinds of 1/f noise behavior can be distinguished which point toward a different origin. The nature of the 1/f noise is most clearly identified by inspecting the variation of the frequency exponent with forward bias. On the one hand, what could be called “peripheral” or “surface” 1/f noise shows a frequency exponent which reduces with increasing forward current, a trend which is also observed for the corresponding ideality factor. When the 1/f noise is predominantly generated in the volume of the material (bulk origin), a more or less constant frequency exponent is found. It is also concluded that in many cases, no unique area or perimeter dependence is found when comparing the noise power spectral density of diodes with a different geometry. It will finally be shown that there exists a close correlation between the different 1/f noise sources and the different reverse current components, which are a sensitive function of the starting material characteristics and processing details     

1/f noise in CMOS transistors for analog applications

Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits     

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

Forward body biasing is a promising approach for realizing optimum threshold-voltage (V _TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (VF) decreases the depletion width (X _DEP) in the channel region, it reduces V _TH rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small X _DEP ) at low V _TH notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for |VF| should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing.     

A dynamic-threshold SOI device with a J-FET embedded sourcestructure and a merged body-bias-control transistor. I. A J-FET embeddedsource structure properties

The floating-body effects in SOI CMOSFETs are fully suppressed by embedding a J-FET source structure immediately beneath the source/drain junction. The drain of the J-FET consists of a Schottky barrier diode; the holes generated in the body can easily be ejected into the source through the forward-biasing of this diode. The source-drain breakdown voltage and drain-induced barrier-lowering characteristics of this device are the same as those of a bulk device. With this structure, the body potential syncrhronously couples to the gate bias in the dynamic mode without potential hysteresis when the body-to-source resistance is properly designed. The inverter-chain delay time should be 45% of that of a bulk device operating at 1 V without an excess load     

1/f noise as a reliability estimation for solar cells

The 1/f noise from a forward biased dark solar cell is a non-destructive reliability estimation. The experimentally observed 1/f noise is compared with Kleinpenning's one-dimensional calculations for p-n diodes. At medium and low currents the 1/f noise of n⁺-p solar cells is about 50 times as large as predicted. Such deviations can be caused by non-uniformities in the large junction area. Local areas with lower built-in potentials at the junction lead to hot spots and reduced reliability. At large currents, reliability problems due to possible poor contacts can be studied from the proportionality between the noise and the square of the current.     

Analysis of laser diodes as transmitter and preamplifiers in timecompression multiplexing systems

It is proposed that a laser diode used as a transmitter in the transmission mode be used as a low bias current preamplifier in the receiving mode for time compression multiplexing transmission. By adopting the low bias current approach, the preamplifier is wavelength and polarization independent. The maximum bias current is determined to be about 0.5 I_th (I_th=threshold current) by experiments. A transmission experiment at 3.5 Mb/s reveals that about 4 dB of improvement in receiver sensitivity can be obtained by using a laser preamplifier at I=0.54 I_th when compared to an unbiased laser. The receiver sensitivity of the proposed configuration (laser amplifier at low bias current and photodiode) is estimated by considering the laser preamplifier noise and circuit noise. The laser preamplifier noise is calculated by treating the laser as a traveling wave amplifier with highly reflecting facets