On the avalanche multiplication mechanism in SPICE simulations of high-frequency bipolar transistors with thin basewidths and low breakdown voltages

A very simple subcircuit model for SPICE simulation of bipolar transistors affected by the avalanche multiplication mechanism is presented. The currently available models for bipolar transistors in circuit simulators do not consider this effect, which can lead to serious simulation errors when high-frequency thin basewidths transistors with low and soft breakdown voltages are simulated. The simulated results predicted by SPICE with the proposed subcircuit are compared with the measured data obtained from several transistors with low and soft breakdown voltages and a good agreement is reported.     

Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance

This paper investigates the electro-thermal stress-induced performance degradation of a cascode low-noise amplifier built using advanced InGaP/GaAs heterojunction bipolar transistors. Changes in device characteristics due to the electro-thermal stress are examined experimentally. SPICE Gummel-Poon model parameters extracted from the pre- and post-stress HBT measurement data are then used in Cadence SpectreRF simulator to study the impact of the electro-thermal stress on the InGaP/GaAs LNA’s RF performance.     

Oxygen implantation to suppress parasitic bipolar action in CMOS

Oxygen implantation and subsequent epitaxial silicon deposition have been developed to improve CMOS latchup prevention through reducing the current gains of parasitic bipolar transistors. The buried oxygen implanted layer is well confined, and defects do not extend into the epitaxial silicon layer. The device characteristics of the n- and p-MOSFETs fabricated on a wafer with the oxygen implantation are therefore not affected by the buried implanted layer. The oxygen implanted layer can reduce the minority-carrier lifetime and hence decrease the current gain of the lateral parasitic bipolar transistor. In addition, it introduces a potential barrier which decreases the current collected at the frontside contact of the vertical parasitic bipolar transistor. The common base current gain is reduced by 50% and 80% for the lateral and the vertical parasitic bipolar transistors, respectively. As a consequence, the CMOS latchup immunity is significantly improved     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

A compact physical large-signal model for high-speed bipolar transistors at high current densities—Part I: One-dimensional model

A compact physical large-signal transistor model is presented that is suited for simulating high-speed bipolar IC's even if the transistors are operated deeply within the high-current region (including quasi-saturation). Like the well-known and currently used Gummel-Poon model, it is based on the integral charge-control relation (ICCR) proposed by Gummel. However, in the high-current region it shows much better accuracy, especially for high-frequency and switching operation. This is mainly a result of the fact that the transit time (and thus the minority-carrier charge) is chosen as a basic model parameter, which is carefully measured and accurately approximated by analytical expressions throughout the total interesting operating range. In Part I of the work, presented here, the model and its parameters are described for the one-dimensional case. Its validity is verified by comparison with exact numerical transistor simulations of both the dc characteristics and the switching behavior. The simulations are based on doping profiles that are typical of transistors in high-speed IC's. Methods for determination of the model parameters are presented. In Part II [1], the model is extended to the two-dimensional case, i.e., to real transistors. It is experimentally verified by measuring the dc characteristics and the switching behavior of very fast transistors with high transit frequency (fT≈ 7 GHz) and small emitter stripe width. The complete model, which is called HICUM (from "high-current model"), was already implemented in the circuit analysis program SPICE 2.     

一种基于保角变换的环形栅晶体管用作ESD防护器件的建模方法

This paper proposes a novel technique for modeling the electrostatic discharge （ESD） characteristic of the enclosed-gate layout transistors （ELTs）. The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELF is decomposed into edge and comer transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM （Berkeley Short- channel IGFET Model）. Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.     

Physics-based minority charge and transit time modeling for bipolartransistors

It has been well known for many years that the transit time model used in the SPICE Gummel-Poon model (SGPM) is not adequate for reliable design of circuits operating either at high current densities (including quasi-saturation), which is often the case in high-speed integrated circuits, or at low voltages, which is important for low-power applications. In addition, extraction of the SGPM's transit time model parameters is often very difficult and time consuming. Although various proposals for modeling the transit time were published in the past, most of them are not suited for compact transistor models required in circuit simulation from a numerical, parameter extraction and lateral scaling point of view. In this paper, a set of minority charge and transit time equations is derived which are physics-based and laterally scaleable as well as suitable for incorporation into compact models. Experimental results of the new model are presented in terms of transit time and transit frequency versus bias (I_C, V_CE), geometry, and temperature, showing excellent agreement for different types of silicon homojunction bipolar transistors     

VBIC95, the vertical bipolar inter-company model

This paper details the VBIC95 bipolar junction transistor (BJT) model. The model was developed as an industry standard replacement for the SPICE Gummel-Poon (SGP) model, to improve deficiencies of the SGP model that have become apparent over time because of the advances in BJT process technology. VBIC95 is still based on the Gummel-Poon formulation, and thus can degenerate to be similar to the familiar SGP model. However, it includes improved modeling of the Early effect, quasi-saturation, substrate and oxide parasitics, avalanche multiplication, and temperature behavior that can be invoked selectively based on model parameter values     

Modified Gummel-Poon model for susceptibility prediction

This paper describes a new model of the bipolar transistor by which the effects of RF interference on the DC quiescent operating point upset can be computed. It is an improvement of the Gummel-Poon (GP) model used in circuit simulators like SPICE in the sense that it takes into account distributed phenomena excited by RF interference like the DC and AC crowding of the emitter current in the base region. The model, implemented in SPICE, has been experimentally validated and its efficiency has been demonstrated. The model does not require more measurements then those necessary to extract the parameters of the conventional GP model     

A complementary bipolar technology family with a VerticallyIntegrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP^TMI) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies     

Influence of impact-ionization-induced base current reversal onbipolar transistor parameters

In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined     

Physical modeling of lateral scaling in bipolar transistors

The dependence of important transistor characteristics, such as transit frequency, on emitter width and length is modeled on a physical basis. Closed-form explicit analytical equations are derived for modeling the emitter size dependence of the low-current minority charge and transit time, the critical current indicating the onset of high injection in the collector, and the stored minority charge in the collector at high injection. These equations are suited for application in various compact transistor models such as the SPICE Gummel-Poon model (SGPM) as well as the advanced models HICUM and MEXTRAM. As demonstrated by two- and three-dimensional device simulation and measurements, combination of the derived equations with HICUM results in accurate prediction of the characteristics of transistors with variable emitter length and width. As a consequence, the new model makes the conventional transistor library unnecessary and offers bipolar circuit designers the flexibility to use the transistor size that fits the application best     

MODELLA-a new physics-based compact model for lateral p-n-ptransistors

A lateral p-n-p compact model, suitable for computer-aided circuit design purposes, is introduced. In this formulation, called MODELLA, the equivalent circuit topology, analytical equations, and model parameters are derived directly from the physics and structure of the lateral p-n-p. MODELLA incorporates current crowding effects, substrate effects, and a bias-dependent output conductance and it uses the approach to lateral p-n-p high injection modeling whereby the main currents and charges are independently related to bias-dependent minority-carrier concentrations. Model-specific aspects of the parameter determination strategy are discussed; the Ning-Tang resistance determination method, for example, is shown to be highly suitable for lateral p-n-p devices. The effectiveness of this strategy and the improved performance of this physics-based formulation become evident in comparisons between MODELLA and the standard SPICE Gummel-Poon model using measured device characteristics     

Concise transient SPICE model for bipolar power transistor quasi-saturation simulation

A concise transient SPICE model is presented in this paper to predict both the static and the switching behaviour of power transistors, with emphasis placed on quasi-saturation effects. The model is proposed to simulate both ohmic and non-ohmic quasi-saturation phenomena by automatically adjusting the hole injection ratio term. The model incorporates the currently used Gummel-Poon (GP) model and an additional charge-control relation for the transistor's epitaxial collector. The turn-off charge removal phenomenon is not modelled specifically; however, the charge-control equation for the epitaxial collector region may partly simulate this effect where the quasi-saturation region is entered. The validity of the model is verified by comparison between the original SPICE bipolar junction transistor model and experimental data for both DC and turn-on conditions. Methods for determining the model parameters are described.     

Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation

Substrate current injection effects are one of the major risks for smart-power IC functionality, often leading to redesigns. Smart-power ICs for motor control consist of four power transistors in H-bridge configuration and the controlling circuitry on a single chip. During switching of the power stages driving an inductive load (e.g. a motor), parasitic bipolar transistors turn on and inject electrons and holes into the substrate. This leads to a substrate potential shift with the risk of disturbing the functionality of the controlling circuitry or even triggering a latch-up. The substrate potential shift due to minority carrier injection by the lateral parasitic NPN transistor has been measured on a test chip and analyzed by 3D device simulation. The previously calibrated 3D device simulation and the measurements are in good agreement. The influence of protecting measures (substrate contacts) and the backside contact has been investigated experimentally. For the first time, the potential shift due to the parasitic substrate NPN transistor has been measured and simulated in 3D on an entire chip.     

新颖的IGBT SPICE模型及非破坏参数提取和验证

提出并优化了一种和现有SPICE软件如HSPICE完全兼容的IGBT等效电路模型.该模型摒弃了双极晶体管的所谓准静态假设而用精确的双极输运理论进行分析,更符合IGBT的实际工作条件.利用电压控制可变电阻模型等效IGBT的n-外延层的电导调制效应,取得了很好的效果.基于器件的非破坏实测参数以器件物理方程为基础的模型参数提取,计算依据正确,物理意义明确.用该模型计算了IGBT的I-V特性、开关特性等,与实测符合较好,误差不超过8%,此结果比已报道的同类模型要好,且更为简单方便.     

DC modeling and characterization of AlGaAs/GaAs heterojunctionbipolar transistors for high-temperature applications

The large signal dc characteristics of AlGaAs/GaAs heterojunction bipolar transistors (HBT) at high temperatures (27°-300°C) are reported. A high-temperature SPICE model is developed which includes the recombination-generation current components and avalanche multiplication which become extremely important at high temperatures. The effect of avalanche breakdown is also included to model the current due to thermal generation of electron/hole pairs causing breakdown at high temperatures. A parameter extraction program is developed and used to extract the model parameters of HBT's at different temperatures. Fitting functions for the model parameters as a function of temperature are developed. These parameters are then used in the SPICE Ebers-Moll model for the dc characterization of the HBT at any temperature between (27°-300°C)     

Base current reversal phenomenon in a CMOS compatible high gainn-p-n gated lateral bipolar transistor

Base current reversal phenomenon is newly observed in a CMOS compatible high gain n-p-n gated lateral bipolar transistor. We attribute this phenomenon to avalanche generation as verified experimentally and by two-dimensional device simulation. Detailed investigation reveals that: (i) the multiplication ratio increases exponentially with the collector voltage or equivalently the peak field at the surface collector corner; and (ii) the multiplication ratio is independent of not only the low level base-emitter forward biases applied but also the base width of the transistors fabricated by the same process. Design guideline for suppression of the base current reversal has been established such as to fully realize the potential of the gated lateral bipolar transistors, i.e., a very high current gain of 11,600 can be maintained as long as the power supply voltage is less than the critical value of 1.78 V. On the other hand, new application directly employing this phenomenon has been suggested. Comparisons between the base current reversal phenomenon in the gated lateral bipolar transistor and that in the vertical bipolar transistor have also been performed and significant differences between the two have been drawn and have been adequately explained     

Partitioned-charge-based modeling of bipolar transistors for non-quasi-static circuit simulation

The concept of partitioned-charge-based (PC) modeling of bipolar transistors is developed and demonstrated, and shown to be fundamentally superior to conventional quasi-static charge-control modeling, the basis of the common (capacitance-based) Gummel-Poon (GP) equivalent circuit. SPICE transient simulations with PC and GP models are contrasted to show a first-order accounting for non-quasi-static (NQS) delay in the PC model which is not accounted for in the GP model. Additional model contrasts in the small-signal domain, compared with exact ac solutions, confirm the superiority of the PC model, the characterization of which is in fact no more tedious than that of the GP model.     

A quasi-one-dimensional analysis of small-signal current gains in lateral transistors

A small-signal analysis of lateral p-n-p transistors has been made using a quasi-one-dimensional model. This model consists of a lateral p-n-p intrinsic transistor section and a vertical p-n-n⁺-p parasitic transistor section. The effect of the retarding electric field of the n⁺subdiffused layer is incorporated explicitly into the model. Besides, the field-dependent nonunity emitter efficiency of lateral transistors has also been taken into account. From the solutions of continuity equations in the base regions, closed-form expressions for small-signal current gains are obtained in terms of an ac field factor which is defined by the geometry and doping profile of the device. Frequency dependence of current gains evaluated from this analysis compares favorably with the results from an earlier two-dimensional analysis. The simplicity of the model and its reasonably good accuracy are expected to be helpful in the modeling of lateral transistors used in linear integrated circuits.