Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die‐selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die‐selection method is proposed for multi‐layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi‐layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multi‐layer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.     

相邻层冗余共享的三维存储器成品率优化方法

存储裸片堆叠方案和冗余共享策略对提高三维存储器成品率有重要影响.为提高三维存储器的成品率并且减少行列冗余所需的TSVs数量,提出了一种相邻层冗余共享结构.该冗余共享结构使得每层存储裸片的行列冗余不仅能被本层使用,而且能被相邻层使用.并在此结构的基础上,提出了一种新的存储裸片堆叠方案.该方案通过构建存储裸片的选择限制条件,每次选中适合的存储裸片来堆叠三维存储器以充分利用行列冗余.实验结果表明,与国际上同类方法相比,所提方案有效地提高了三维存储器的成品率,并且减少了行列冗余所需的TSVs数量.     

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Enhancing quality of experience using peer‐to‐peer overlay on device‐to‐device communications

With the recent development of LTE‐A/5G technologies, data sharing among mobile devices offer an attractive opportunity to reduce Internet access. However, it requires smart strategies to share the data with low trade‐offs in time, cost, and energy. Several existing schemes offer a super‐peer‐based two‐tier model using a distributed hash table (DHT) organization for smart devices having device‐to‐device (D2D)/Bluetooth/WiFi capabilities. The primary focus of these schemes has been to reduce Internet usage by increased D2D content sharing. However, the real challenge is not in creating a two‐tier model, but evolving an efficient overlay that offers enhanced opportunities for D2D content sharing over the existing model. In this paper, we formulated a P‐median‐based selection of tier‐1 devices in a distribution network and solved it using the Lagrangian relaxation method. The tier‐2 devices become clients seeking content sharing services from tier‐1 devices. A strong motivation in this work is to raise a user's perception of the grade of service known as quality of experience (QoE). We analyzed the challenge for QoE assessment in resource‐constrained smartphones under the proposed model of enhanced D2D communication. Our focus is to establish a framework to evaluate QoE for applications and services over LTE‐A/5G networks with an improved D2D communication level. The simulation and the experimental results validate the claim that substantial improvements in QoE are possible with the proposed mathematical model for selecting and placing tier‐1 mobile devices and maintaining a DHT for D2D communication.     

A Review of Three‐Dimensional Resistive Switching Cross‐Bar Array Memories from the Integration and Materials Property Points of View

Issues in the circuitry, integration, and material properties of the two‐dimensional (2D) and three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic‐level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.     

Dynamic Self‐Repair Architectures for Defective Through‐silicon Vias

Three‐dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through‐silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built‐in self‐test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self‐repair architectures using code‐based and hardware‐mapping based repair.     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

Space‐Time Warp Curve for Synthesizing Multi‐character Motions

This paper introduces a new motion‐synthesis technique for animating multiple characters. At a high level, we introduce a hub‐sub‐control‐point scheme that automatically generates many different spline curves from a user scribble. Then, each spline curve becomes a trajectory along which a 3D character moves. Based on the given curves, our algorithm synthesizes motions using a cyclic motion. In this process, space‐time warp curves, which are time‐warp curves, are embedded in the 3D environment to control the speed of the motions. Since the space‐time warp curve represents a trajectory over the time domain, it enables us to verify whether the trajectory causes any collisions between characters by simply checking whether two space‐time warp curves intersect. In addition, it is possible to edit space‐time warp curves at run time to change the speed of the characters. We use several experiments to demonstrate that the proposed algorithm can efficiently synthesize a group of character motions. Our method creates collision‐avoiding trajectories ten times faster than those created manually.     

基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究

针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D NoC)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D NoC测试的影响,进一步优化3D NoC在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D NoC的测试TSV数量,提高了TSV的利用率。     

Collective laser‐assisted bonding process for 3D TSV integration with NCP

Laser‐assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single‐tier LAB process for 3D through‐silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single‐tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu‐Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.     

Clock Mesh Network Design with Through‐Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.     

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.     

Light‐Coded Digital Crystallinity Patterns Toward Bioinspired 4D Transformation of Shape‐Memory Polymers

Spatially heterogeneous distribution of active components is key to the diverse shape‐morphing behaviors of biological species and their associated functions. Artificial morphing materials employing similar strategies have widened the design space for advanced functional devices. Typically, the spatial heterogeneity is introduced during the material synthesis/fabrication step and cannot be altered afterward. An approach that allows spatio‐selective programming of crystallinity in a shape‐memory polymer (SMP) by a digital photothermal effect is reported. The light‐patternable crystallinity affects greatly the shape morphing behavior. Consequently, a pre‐stretched 2D film with spatial heterogeneity in crystallinity can morph with time into designable 3D permanent shapes, achieving the 4D transformation. This approach utilizes a reprocessible thermoplastic SMP (polylactide) and the programming relies on a physical phase transformation (crystallization) instead of chemical heterogeneity. This allows repeated erasing and reprogramming using the same material, suggesting a versatile and sustainable means for manufacturing advanced morphing devices.     

New TDOA‐Based Three‐Dimensional Positioning Method for 3GPP LTE System

Recently, mobile positioning enhancement has attracted much attention in the 3rd generation partnership project long‐term evolution system. In particular, for urban canyon environments, the need for three‐dimensional (3D) positioning has increased to enable the altitude of users to be measured. For several decades, several time difference of arrival (TDOA‐) based 3D positioning methods have been studied; however, they are only available when at least four evolved Node Bs (eNBs) exist nearby or when all eNBs have the same height. Therefore, in this paper, we propose a new 3D positioning method that estimates the 3D coordinates of a user using three types of two‐dimensional (2D) TDOAs. However, the give inaccurate results owing to the undefined axis of the 2D coordinate plane. Therefore, we propose a novel derivation of the hyperbola equation, which includes the undefined axis coordinate in the 2D hyperbola equation. Then, we propose an interaction algorithm that mutually supplies the undefined axis coordinate of users among 2D TDOAs. By performing extensive simulations, we verify that the proposed method is the only solution applicable by using three eNBs with different heights.     

A Flexible Programmable Memory BIST for Embedded Single‐Port Memory and Dual‐Port Memory

Programmable memory built‐in self‐test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single‐port memory and dual‐port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.     

Dynamic Data Migration in Hybrid Main Memories for In‐Memory Big Data Storage

For memory‐based big data storage, using hybrid memories consisting of both dynamic random‐access memory (DRAM) and non‐volatile random‐access memories (NVRAMs) is a promising approach. DRAM supports low access time but consumes much energy, whereas NVRAMs have high access time but do not need energy to retain data. In this paper, we propose a new data migration method that can dynamically move data pages into the most appropriate memories to exploit their strengths and alleviate their weaknesses. We predict the access frequency values of the data pages and then measure comprehensively the gains and costs of each placement choice based on these predicted values. Next, we compute the potential benefits of all choices for each candidate page to make page migration decisions. Extensive experiments show that our method improves over the existing ones the access response time by as much as a factor of four, with similar rates of energy consumption.     

Yield enhancement techniques for 3-dimensional random access memories

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.     

Flexible Crossbar‐Structured Phase Change Memory Array via Mo‐Based Interfacial Physical Lift‐Off

Inorganic phase change memories (PCMs) have attracted substantial attention as a next‐generation storage node, due to their high‐level of performance, reliability, and scalability. To integrate the PCM on plastic substrates, the reset power should be minimized to avoid thermal degradation of polymers and adjacent cells. Additionally, flexible phase change random access memory remains unsolved due to the absence of the optimal transfer method and the selection device. Here, an Mo‐based interfacial physical lift‐off transfer method is introduced to realize a crossbar‐structured flexible PCM array, which employs a Schottky diode (SD) selection device and conductive filament PCM storage node. A 32 × 32 parallel array of 1 SD‐1 CFPCM, which utilizes a Ni filament as a nanoheater for low power phase transition, is physically exfoliated from the glass substrate at the face‐centered cubic/body‐centered cubic interface within the sacrificial Mo layer. First principles density functional theory calculations are utilized to understand the mechanism of the Mo‐based exfoliation phenomena and the observed metastable Mo phase. The flexible 1 SD‐1 CFPCM shows reliable operations (e.g., large resistance ratio of 17, excellent endurance over 100 cycles, and long retention over 10⁴ s) with excellent flexibility. Furthermore, the random access operation is confirmed by addressing tests of characters “KAIST.”