Novel Bumping Process for Solder on Pad Technology

A novel bumping process using solder bump maker is developed for the maskless low‐volume solder on pad (SoP) technology of fine‐pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low‐volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low‐volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is successfully formed.     

Fine‐Pitch Solder on Pad Process for Microbump Interconnection

A cost‐effective and simple solder on pad (SoP) process is proposed for a fine‐pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60‐μm pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine‐pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine‐pitch SoP process and evaluate the fine‐pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45‐μm diameter and 60‐μm pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine‐pitch SoP and microbump interconnection using a screen printing process.     

Optimization of Material and Process for Fine Pitch LVSoP Technology

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low‐volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μm, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine‐pitch interconnection of a Cu pillar in the semiconductor packaging field.     

HV‐SoP Technology for Maskless Fine‐Pitch Bumping Process

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip‐chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine‐pitch solder bumping has been widely studied. In this study, high‐volume solder‐on‐pad (HV‐SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV‐SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine‐pitch flip‐chip bonding.     

Novel Maskless Bumping for 3D Integration

A novel, maskless, low‐volume bumping material, called solder bump maker, which is composed of a resin and low‐melting‐point solder powder, has been developed. The resin features no distinct chemical reactions preventing the rheological coalescence of the solder, a deoxidation of the oxide layer on the solder powder for wetting on the pad at the solder melting point, and no major weight loss caused by out‐gassing. With these characteristics, the solder was successfully wetted onto a metal pad and formed a uniform solder bump array with pitches of 120 µm and 150 µm.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Interconnection Technology Based on InSn Solder for Flexible Display Applications

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip‐chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C.     

Abnormal growth of tin whiskers in a Sn3Ag0.5Cu0.5Ce solder ball grid array package

It has been discovered for the first time that Sn whiskers appeared in Sn3Ag0.5Cu0.5Ce solder joints of ball grid array (BGA) packages after storage at room temperature (natural aging) for less than 3 days and they grew at a high rate of 2.9 ?/sec. In one particular case, whiskers even formed after 1 day of storage at an extremely high growth rate of 8.6 ?/sec. Experimental investigations showed that a number of CeSn₃ clusters existed in the Sn3Ag0.5Cu0.5Ce solder matrix after the reflow process. Further natural aging in air for several days caused the CeSn₃ phases to oxidize rapidly, from which many Sn whiskers sprouted and grew to a length of hundreds of micrometers. The most commonly observed whiskers have been long fiber-shaped ones of 0.1 μm to 0.3 μm in diameter (type I), while short whiskers larger than 1 μm in diameter can also be found (type II). Here in our case, the surface oxide of the CeSn₃ phase possessed a higher content of Ce than of Sn, which implied that a Ce-depleted region (nearly of pure Sn) was left beneath the oxide layer. The abnormal whisker growth was attributed to the compressive stress squeezing the Sn atoms in the Ce-depleted region of CeSn₃ phase out of the oxide layer.     

Characterizing metallurgical reaction of Sn3.0Ag0.5Cu composite solder by mechanical alloying with electroless Ni-P/Cu under-bump metallization after various reflow cycles

Electroless Ni-P/Cu under-bump metallization (UBM) is widely used in electronics packaging. The Sn3.0Ag0.5Cu lead-free composite solder pastes were produced by a mechanical alloying (MA) process doped with Cu₆Sn₅ nanoparticles. In this study, the detailed interfacial reaction of Sn3.0Ag0.5Cu composite solders with EN(P)/Cu UBM was investigated after reflow. A field-emission scanning electron microscope (FESEM) was employed to analyze the interfacial morphology and microstructure evolution. The intermetallic compounds (IMCs) formed at the interface between the Sn3.0Ag0.5Cu composite solders and EN(P)/Cu UBM after one and three reflows were mainly (Ni_1−x,Cu_x)₃Sn₄ and (Cu_1−y,Ni_y)₆Sn₅. However, only (Ni_1−x,Cu_x)₃Sn₄ IMC was observed after five reflows. The elemental distribution near the interfacial region was evaluated by an electron probe microanalyzer (EPMA) as well as field-emission electron probe microanalyzer (FE-EPMA). Based on the observation and characterization by FESEM, a EPMA, and an FE-EPMA, the reaction mechanism of interfacial phase transformation between Sn3.0Ag0.5Cu composite solders and EN(P)/Cu UBM after various reflow cycles was discussed and proposed.     

Revealing the nucleation and growth mechanism of a novel solder developed from Sn-3.5Ag-0.5Cu nanoparticles by a chemical reduction method

Sn-3.5Ag-0.5Cu nanoparticles were synthesized by chemical precipitation with NaBH₄. By using x-ray diffraction and transmission and scanning electron microscopy, the microstructural characteristics of particle growth were evaluated. The results indicated that the primary particles after precipitation were (Ag,Cu)₄Sn, with a size of 4.9 nm. (Ag,Cu)₄Sn was transformed into (Ag,Cu)₃Sn, when the total amount of Sn contributed from both (Ag,Cu)₄Sn and Sn covering the (Ag,Cu)₄Sn overtook that of (Ag,Cu)₃Sn. The final particle size of polycrystalline particles was 42.1 nm owing to the depletion of Sn atoms in the solution. Nucleation and growth mechanisms of Sn-3.5Ag-0.5Cu nanoparticles are also discussed and proposed.     

Privacy‐preserving authentication scheme for on‐road on‐demand refilling of pseudonym in VANET

Privacy in Vehicular Ad Hoc Networks (VANET) is fundamental because the user's safety may be threatened by the identity and the real‐time spatiotemporal data exchanged on the network. This issue is commonly addressed by the use of certified temporal pseudonyms and their updating strategies to ensure the user's unlinkability and anonymity. IEEE 1609.2 Standard specified the process of certifying pseudonym along with certificates structure. However, the communication procedure between the certifying authority and the requesting vehicle was not defined. In this paper, a new privacy‐preserving solution for pseudonym on‐road on‐demand refilling is proposed where the vehicle anonymously authenticates itself to the regional authority subsidiary of the central trusted authority to request a new pseudonyms pool. The authentication method has two phases, the first one uses anonymous tickets, and the second one is a challenge‐based authentication. The anonymous tickets are certificates that do not include the identity of the user. Instead, it contains a reference number and the certifying authority signature. The challenge authentication is identity‐less to preserve the privacy, yet it is used to prevent the misuse of tickets and the impersonation of its owner. Our proposed scheme is analyzed by the use of Burrows, Abadi and Needham (BAN) logic to demonstrate its correctness. It is also specified and checked by using the Security Protocol ANimator (SPAN) and the Automated Validation of Internet Security Protocols and Applications (AVISPA) tools. The logical demonstration proved that this privacy‐preserving authentication is assured. The SPAN and AVISPA tools illustrated that it is resilient to security attacks.     

Demonstration and Characterization of Sn-3.0Ag-0.5Cu/ Sn-57Bi-1Ag Combination Solder for 3-D Multistack Packaging

A combination solder of Sn-3.0Ag-0.5Cu (numbers are all in weight percent unless specified otherwise) wrapped by Sn-57Bi-1Ag was tested for application to three-dimensional (3-D) multistack packaging. The experimental variables controlled were the reflow peak temperatures (170, 185, 200, and 230°C), the reflow cycles (up to four times), and the mask which controls the amount of Sn-57Bi-1Ag solder paste (two sizes). We demonstrate and evaluate the combination solder structure, focusing on microstructural changes and the shear strength. The degree of mixing in the combination solder, which is enhanced by an increase in the reflow peak temperature, is independent of the number of reflow cycles. The ball shear strength and the lab shear strength both increased with increases in the reflow peak temperatures. This behavior is explained by the amount of the brittle Bi phase that constitutes the eutectic Sn-Bi phase.     

New Path‐Setup Method for Optical Network‐on‐Chip

With high bandwidth, low interference, and low power consumption, optical network‐on‐chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path‐setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non‐blocking optical router is designed to support the new method. The simulation results show the new path‐setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot‐I, and hotspot‐II traffic patterns, respectively. The end‐to‐end delay performance is also improved.     

Standardized testing conditions for satellite communications on‐the‐move (SOTM) terminals

Performance validation of Satcom on‐the‐move (SOTM) terminals is becoming more important as the satellite operators continue to recognize the negative influence of suboptimal terminals on their satellite networks. Traditionally, SOTM testing is performed with actual operational satellites in field tests, which lack repeatability. The capability to repeat the conditions in which SOTM terminals are tested is important, especially when the performance of multiple terminals is compared. This contribution describes how the qualification test of SOTM terminals can be conducted in a laboratory environment so that repeatability can be ensured. A major advantage of a laboratory environment is the ability to test the complete terminal as if it was in the field of operation, yet without the involvement of real satellites effectively reducing the costs of testing. The main contributions of this paper are motion and shadowing profiles suitable for standardization of SOTM testing. Standardization of such profiles is necessary to guarantee a fair comparison of the performance of different terminals. Moreover, the paper presents the methodology for testing SOTM terminals at the Fraunhofer Facility for Over‐the‐air Research and Testing, * * * https://www.iis.fraunhofer.de/en/profil/standorte/forte.html the procedure used to obtain the proposed profiles and results of testing a Ka‐band SOTM terminal, taken as an example.     

Nonmulberry Silk Based Ink for Fabricating Mechanically Robust Cardiac Patches and Endothelialized Myocardium‐on‐a‐Chip Application

Bioprinting holds great promise toward engineering functional cardiac tissue constructs for regenerative medicine and as drug test models. However, it is highly limited by the choice of inks that require maintaining a balance between the structure and functional properties associated with the cardiac tissue. In this regard, a novel and mechanically robust biomaterial‐ink based on nonmulberry silk fibroin protein is developed. The silk‐based ink demonstrates suitable mechanical properties required in terms of elasticity and stiffness (≈40 kPa) for developing clinically relevant cardiac tissue constructs. The ink allows the fabrication of stable anisotropic scaffolds using a dual crosslinking method, which are able to support formation of aligned sarcomeres, high expression of gap junction proteins as connexin‐43, and maintain synchronously beating of cardiomyocytes. The printed constructs are found to be nonimmunogenic in vitro and in vivo. Furthermore, delving into an innovative method for fabricating a vascularized myocardial tissue‐on‐a‐chip, the silk‐based ink is used as supporting hydrogel for encapsulating human induced pluripotent stem cell derived cardiac spheroids (hiPSC‐CSs) and creating perfusable vascularized channels via an embedded bioprinting technique. The ability is confirmed of silk‐based supporting hydrogel toward maturation and viability of hiPSC‐CSs and endothelial cells, and for applications in evaluating drug toxicity.     

Co‐deposited Cu(I) Complex for Tri‐layered Yellow and White Organic Light‐Emitting Diodes

Four compounds 4‐[3,6‐di(carbazol‐9‐yl)carbazol‐9‐yl]isoquinoline (TCIQ), 3‐[3,6‐di(carbazol‐9‐yl)carbazol‐9‐yl]pyridine (TCPy), 4‐(carbazol‐9‐yl)isoquinoline (4CIQ), and 3‐(carbazol‐9‐yl)pyridine (CPy) containing pyridyl or isoquinolyl were designed and synthesized to co‐deposition with copper iodide (CuI) to form luminescent Cu(I) complex doped film in situ, which could be utilized as the emissive layer in organic light‐emitting diodes (OLEDs). It is found that simple tri‐layered yellow and white OLEDs can be achieved by co‐depositing CuI and TCIQ with tuning ratios. The compound TCIQ serves a dual role as both a ligand for forming the emissive Cu(I) complex and as a host matrix for the formed emitter in yellow OLEDs, and a third role as a blue emitter in white OLEDs.     

A Non‐rare‐Earth Ions Self‐Activated White Emitting Phosphor under Single Excitation

White light phosphors have many potential applications such as solid‐state lighting, full color displays, light source for plant growth, and crop improvement. However, most of these phosphors are rare‐earth‐based materials which are costly and would be facing the challenge of resource issue due to the extremely low abundance of these elements on earth. A new white color composite consisted of a graphitic‐phase nitrogen carbon (g‐C₃N₄) treated with nitric acid and copper‐cysteamine Cu₃Cl(SR)₂ is reported herein. Under a single wavelength excitation at 365 nm, these two materials show a strong blue and red luminescence, respectively. It is interesting to find that the white light emission with a quantum yield of 20% can be obtained by mixing these two self‐activated luminescent materials at the weight ratio of 1:1.67. Using a 365 nm near‐ultraviolet chip for excitation, the composite produces a white light‐emitting diode that exhibits an excellent color rendering index of 94.3. These white‐emitting materials are environment friendly, easy to synthesize, and cost‐effective. More importantly, this will potentially eliminate the challenge of rare earth resources. Furthermore, a single chip is used for excitation instead of a multichip, which can greatly reduce the cost of the devices.     

Memristive Logic‐in‐Memory Integrated Circuits for Energy‐Efficient Flexible Electronics

A memristive nonvolatile logic‐in‐memory circuit can provide a novel energy‐efficient computing architecture for battery‐powered flexible electronics. However, the cell‐to‐cell interference existing in the memristor crossbar array impedes both the reading process and parallel computing. Here, it is demonstrated that integration of an amorphous In‐Zn‐Sn‐O (a‐IZTO) semiconductor‐based selector (1S) device and a poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3)‐based memristor (1M) on a flexible substrate can overcome these problems. The developed a‐IZTO‐based selector device, having a Pd/a‐IZTO/Pd structure, exhibits nonlinear current–voltage (I–V) characteristics with outstanding stability against electrical and mechanical stresses. Its underlying conduction mechanism is systematically determined via the temperature‐dependent I–V characteristics. The flexible one‐selector?one‐memristor (1S–1M) array exhibits reliable electrical characteristics and significant leakage current suppression. Furthermore, single‐instruction multiple‐data (SIMD), the foundation of parallel computing, is successfully implemented by performing NOT and NOR gates over multiple rows within the 1S–1M array. The results presented here will pave the way for development of a flexible nonvolatile logic‐in‐memory circuit for energy‐efficient flexible electronics.     

Simulation analyses of weighted fair bandwidth‐on‐demand (WFBoD) process for broadband multimedia geostationary satellite systems

Advanced resource management schemes are required for broadband multimedia satellite networks to provide efficient and fair resource allocation while delivering guaranteed quality of service (QoS) to a potentially very large number of users. Such resource management schemes must provide well‐defined service segregation to the different traffic flows of the satellite network, and they must be integrated with some connection admission control (CAC) process at least for the flows requiring QoS guarantees. Weighted fair bandwidth‐on‐demand (WFBoD) is a resource management process for broadband multimedia geostationary (GEO) satellite systems that provides fair and efficient resource allocation coupled with a well‐defined MAC‐level QoS framework (compatible with ATM and IP QoS frameworks) and a multi‐level service segregation to a large number of users with diverse characteristics. WFBoD is also integrated with the CAC process. In this paper, we analyse via extensive simulations the WFBoD process in a bent‐pipe satellite network. Our results show that WFBoD can be used to provide guaranteed QoS for both non‐real‐time and real‐time variable bit rate (VBR) flows. Our results also show how to choose the main parameters of the WFBoD process depending on the system parameters and on the traffic characteristics of the flows. Copyright © 2005 John Wiley & Sons, Ltd.     

Extended Trench Gate Superjunction Lateral Power MOSFET for Ultra‐Low Specific on‐Resistance and High Breakdown Voltage

In this paper, a lateral power metal–oxide–semiconductor field‐effect transistor with ultra‐low specific on‐resistance is proposed to be applied to a high‐voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt‐implanted p‐drift layer assists in the full depletion of the n‐drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n‐drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in R_on.sp and a 16% improvement in BV.