Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

An all digital PLL with an active inductor DCO for LTE applications in 0.13 μm CMOS

In this paper, we propose a low-power all digital phase-locked loop with a wide input range, and a high resolution TDC that uses phase-interpolator and a time amplifier. The resolution of the proposed TDC is improved by using a phase-interpolator which divides the inverter delay time and the time amplifier which extends the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is improved by using a fine resolution DCO with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range and to operate at a low-power, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally in order to compensate for gain variations. The die area of the ADPLL is 0.8 mm² using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is −120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm². The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is ?110.17 dBc/Hz at 1 MHz offset.     

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm². The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.     

A 5 GHz 90-nm CMOS all digital phase-locked loop

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of −125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm² and the current consumption is 30 mA from a 1.2 V supply.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.     

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm² . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.     

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation

A digitally controlled oscillator (DCO) to be used in an all-digital phase-locked loop (PLL) is presented which offers a wide operating frequency range, a monotonic gain curve, and compensation for instantaneous supply voltage variation. The monotonic and wide oscillation frequency is achieved by interpolating at the fine tuning block between two nodes selected from a coarse delay line. Supply voltage compensation is obtained by dynamically adjusting the strength of the feedback latch of the delay cell in response to the change of the supply voltage.      

A wide-range VCO with an automatic frequency,amplitude and gain calibration loop

This paper presents a wide tuning range VCO with an automatic frequency, amplitude and gain calibration loop. To cover the wide tuning range, the automatic frequency calibration (AFC) loop is used. In addition, to provide the optimum Negative-Gm to the LC tank in a wide frequency range, the number of active Negative-Gm circuits is designed to be switched digitally based on the target frequency. Also, the VCO gain should be calibrated digitally to compensate for the gain variation. The VCO tuning range is 2.6 GHz, from 1.7 to 4.3 GHz, and the power consumption is 2–4 mA from a 1.8 V supply. The measured VCO phase noise is −120 dBc/Hz at 1 MHz offset.     

A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.     

A Wide Tuning-Range CMOS VCO With a Differential Tunable Active Inductor

By utilizing a differential tunable active inductor for the LC-tank, a wide tuning-range CMOS voltage-controlled oscillator (VCO) is presented. In the proposed circuit topology, the coarse frequency tuning is achieved by the tunable active inductor, while the fine tuning is controlled by the varactor. Using a 0.18-$muhbox m$CMOS process, a prototype VCO is implemented for demonstration. The fabricated circuit provides an output frequency from 500 MHz to 3.0 GHz, resulting in a tuning range of 143% at radio frequencies. The measured phase noise is from$-$101 to$-$118 dBc/Hz at a 1-MHz offset within the entire frequency range. Due to the absence of the spiral inductors, the fully integrated VCO occupies an active area of$hbox 150times hbox 300 muhbox m^2$.     

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

CMOS数控振荡器设计

设计并讨论了一种新颖的完全基于CMOS静态逻辑反相器设计的数字控制振荡器DCO结构(Digitally-Controlled Oscillator),这种数字控制振荡器采用全数字电路构成,较之LC振荡器更加易于设计和制造,适合于高频高性能数字锁相环的应用。电路结构的仿真采用Spectre仿真器,基于STMicroelectronics CMOS 90nm工艺,在1.2V电源电压下实现了1GHz～6GHz的数控振荡频率变化范围,功耗为0.1mW～3mW,10MHz的频率偏移处的相位噪音约为-114dBc/Hz。     

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9–7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.     

An X‐Band Carbon‐Doped InGaP/GaAs Heterojunction Bipolar Transistor MMIC Oscillator

This paper addresses a fully‐integrated low phase noise X‐band oscillator fabricated using a carbon‐doped InGaP heterojunction bipolar transistor (HBT) GaAs process with a cutoff frequency of 53.2 GHz and maximum oscillation frequency of 70 GHz. The oscillator circuit consists of a negative resistance generating circuit with a base inductor, a resonating emitter circuit with a microstrip line, and a buffering resistive collector circuit with a tuning diode. The oscillator exhibits 4.33 dBm output power and achieves ?127.8 dBc/Hz phase noise at 100 kHz away from a 10.39 GHz oscillating frequency, which benchmarks the lowest reported phase noise achieved for a monolithic X‐band oscillator. The oscillator draws a 36 mA current from a 6.19 V supply with 47.1 MHz of frequency tuning range using a 4 V change. It occupies a 0.8 mm × 0.8 mm die area.     

一种采用有源电感的可调增益小面积超宽带低噪声放大器

设计了一款采用可调谐有源电感（TAI）的可调增益的小面积超宽带低噪声放大器(LNA),输入级采用共基极结构,输出级采用射随器结构,分别实现了宽带输入和输出匹配;放大级采用带有反馈电阻的共射共基结构以取得宽的带宽,并采用TAI作负载,通过调节TAI的多个外部偏压使LNA的增益可调。结果表明,该LNA在2~9GHz的频带内,通过组合调节有源电感调节端口的偏压可实现S21在16.5~21.1dB的连续可调;S11小于-14.7dB;S22小于-19.3dB;NF小于4.9dB;芯片面积仅为0.049mm2。     

A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation

A 2.4 GHz high-linearity low-phase-noise cross-coupled CMOS LC voltage-controlled oscillator(VCO) is implemented in standard 0.18-μm CMOS technology.An equalization structure for tuning sensitivity base on the three-stage distributed biased switched-varactor bank and the differential switched-capacitor bank is adopted to reduce the variations of the VCO gain,achieve high linearity,and optimize the phase-noise performance.Compared to the conventional VCO,the proposed VCO has more constant gain over the en...     

CMOS source degenerated differential active inductor

A new CMOS source degenerated differential active inductor is proposed. The proposed differential active inductor required only six transistors or more for proper operation. It is very compact compared to a conventional differential active inductor that was design using two differential transconductors and which requires at least ten transistors. The proposed active inductor was fabricated using Silterra 0.18 mum CMOS process for demonstration. Measurement results show that the proposed active inductor has a wide tuning range with a maximum resonance frequency of 7.85 GHz.