A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.     

Achieving low capture and shift power in linear decompressor-based test compression environment

Growing test data volume and excessive power dissipation are two major issues in testing of very large scale integrated (VLSI) circuits. Most previous low power techniques cannot work well with test-data compression schemes. Even if some low power methods can be applied in a test compression environment, they cannot reduce shift power and capture power simultaneously. This paper presents a new low shift-in power scan testing scheme in linear decompressor-based test compression environment. By dividing the test cubes into two kinds of blocks: non-transitional (low toggles) and transitional (with toggles) and feeding scan chains with these blocks through a novel DFT architecture, this approach can effectively reduce the quantity of transitions while scanning-in a test pattern. A low capture and shift-out power X-filling method compatible with the scan testing scheme is also proposed. The X-filling method assigns an interdependent X-bits set at each run and achieves significant power reduction. Interestingly, in the comprehensive strategy, capture power reduction agrees with shift-out power reduction to a certain extent. Experimental results on the larger ISCAS'89 and ITC'99 benchmark circuits show that the holistic strategy can reduce test power in shift cycles and capture cycles significantly under the constraint of certain compression ratio.     

一种低功耗双重测试数据压缩方案

随着集成电路制造工艺的发展,VLSI（Very Large Scale Integrated）电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗.     

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.     

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design

The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.     

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

Capture-power-aware test data compression using selective encoding

Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The “don’t-care” bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution.     

Modified Selective Huffman Coding for Optimization of Test Data Compression,Test Application Time and Area Overhead

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the proposed scheme gives the better test data compression compared to very recently proposed encoding schemes for any test set. It is clearly demonstrated with a large number of experimental results that the proposed scheme improves the test data compression, reduces overall test application time and on-chip area overhead compared to other Huffman code based schemes.     

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits.     

A step-down boosted-wordline scheme for 1-V battery-operated fastSRAM's

Fast and low-power circuit techniques for battery-operated low-voltage SRAM's are described. To shorten the read access time with low power dissipation, the step-down boosted-wordline scheme, which is combined with current-sense amplifiers, is proposed. Boosting a selected-wordline voltage shortens the bitline delay before the stored data are sensed. The power dissipation while selecting a wordline is suppressed by stepping down the selected-wordline potential. Moreover, to reduce the standby power, a switched-capacitor-type boosted-pulse generator, which is controlled by an address transition detection (ATD) signal, is used. A 61 kword×16-bit organization SRAM test chip was fabricated using the 0.5-μm multithreshold-voltage CMOS (MTCMOS) process. The power dissipation in the memory array is reduced to 57% (1 mW) at 10 kHz operation in comparison with the conventional boosted-wordline scheme     

Simultaneous reduction in volume of test data and power dissipationfor systems-on-a-chip

Reasons for current trade-off of test data volume for scan power dissipation in system-on-chip (SOC) testing is investigated. The conflict between the existing compression method and scan power minimisation technique is understood and it is proved that by using a new compression method this trade-off is unnecessary. When the new compression method is combined with scan latch reordering, savings of up to 97% in peak power and 99% in average power, as well as compression ratios of up to 95% are possible     

MICRO: a new hybrid test data compression/decompression scheme

To overcome the limitation of the automatic test equipment (ATE), test data compression/decompression schemes become a more important issue of testing for a system-on-chip (SoC). In order to alleviate the limitation of previous works, a new hybrid test data compression/decompression scheme for an SoC is developed. The new scheme is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed scheme, called the Modified Input reduction and CompRessing One block (MICRO), uses the modified input reduction, the one block compression, a novel mapping, and reordering algorithms. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed scheme leads to high-compression ratio with low-hardware overhead. Experimental results on ISCAS '89 and ITC '99 benchmark circuits prove the efficiency of the new method.     

Low-power chip interconnection by dynamic termination

A low-power dynamic termination scheme is proposed and demonstrated as a way to reduce power dissipation for high-speed data transport. In this scheme, the transmission lines are terminated only if the signals change. The gate of a switching MOS transistor connected to a termination resistor is driven by differentiating the transmission signal with a resistor and a capacitor. The power dissipation of the terminating resistor can be reduced to 1/5 in the conventional determination scheme, and overshoot can be reduced to 1/5 that in the open scheme. This scheme is promising for use with palm-top equipment, facilitating high-speed low power operation     

A current-sensed high-speed and low-power first-in-first-out memoryusing a wordline/bitline-swapped dual-port SRAM cell

First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words × 8-bits FIFO memory test chip, fabricated with a 0.6-μm CMOS process (a short effective channel length of 0.35 μm is available for both the nMOS and pMOS), has demonstrated the 140-MHz operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 μW and that at 100-MHz dual-port operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern)     

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s _max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s _max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s _max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

We present an analysis of test application time for test data compression techniques that are used for reducing test data volume and testing time in system-on-a-chip (SOC) designs. These techniques are based on data compression codes and on-chip decompression. The compression/decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC. We show via analysis as well as through experiments that the proposed scheme reduces testing time and allows the use of a slower tester. Results on test application time for the ISCAS'89 circuits are obtained using an ATE testbench developed in VHDL to emulate ATE functionality.     

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosinetransform core processor with variable threshold-voltage (VT)scheme

A 4 mm², two-dimensional (2-D) 8×8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V _DD-V_th design space is also studied     

A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition

An alternative image decomposition method that exploits prediction via nearby pixels has been integrated on the CMOS image sensor focal plane. The proposed focal plane decomposition is compared to the 2-D discrete wavelet transform (DWT) decomposition commonly used in state of the art compression schemes such as SPIHT and JPEG2000. The method achieves comparable compression performance with much lower computational complexity and allows image compression to be implemented directly on the sensor focal plane in a completely pixel parallel structure. A CMOS prototype chip has been fabricated and tested. The test results validate the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate with much lower data readout volume. The features of the proposed decomposition scheme also benefit real-time, low rate and low power applications.      

Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.     

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells