Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide,High‐k,and Layered Dielectrics

Thin dielectric films are essential components of most micro‐ and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO₂, HfO₂, and Al₂O₃), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new‐concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.     

Recent progress of (Ba,Sr)TiO<Subscript>3</Subscript> thin films for tunable microwave devices

The (Ba_1−xSr_x)TiO₃ (BST) ferroelectric thin films exhibit outstanding dielectric properties, even at high frequencies (>1 GHz), and large, electric-field dielectric tunability. This feature makes them suitable for developing a new class of tunable microwave devices. The dielectric properties and dielectric tuning property of BST thin films are closely related to the film compositions, substrate types, and post-deposition process. The successful implementation of BST films as high-frequency dielectrics in electrically tunable microwave devices requires a detailed understanding of both their processing and material properties. This paper will review the recent progress of BST thin films as active dielectrics for tunable microwave devices. The technical aspects of BST thin films, such as processing methods, post-annealing process, film compositions, film stress, oxygen defects, and interfacial structures between film and substrate, are briefly reviewed and discussed with specific samples from the recent literature. The major issues requiring additional investigations to improve the dielectric properties of BST thin films for tunable microwave applications are also discussed.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1E11 eV^-1cm^-2), gate leakage property (3.6E3 A/cm^2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.     

Hexagonal Boron Nitride–Enhanced Optically Transparent Polymer Dielectric Inks for Printable Electronics

Solution‐processable thin‐film dielectrics represent an important material family for large‐area, fully‐printed electronics. Yet, in recent years, it has seen only limited development, and has mostly remained confined to pure polymers. Although it is possible to achieve excellent printability, these polymers have low (≈2–5) dielectric constants (ε_r). There have been recent attempts to use solution‐processed 2D hexagonal boron nitride (h‐BN) as an alternative. However, the deposited h‐BN flakes create porous thin‐films, compromising their mechanical integrity, substrate adhesion, and susceptibility to moisture. These challenges are addressed by developing a “one‐pot” formulation of polyurethane (PU)‐based inks with h‐BN nano‐fillers. The approach enables coating of pinhole‐free, flexible PU+h‐BN dielectric thin‐films. The h‐BN dispersion concentration is optimized with respect to exfoliation yield, optical transparency, and thin‐film uniformity. A maximum ε_r ≈ 7.57 is achieved, a two‐fold increase over pure PU, with only 0.7 vol% h‐BN in the dielectric thin‐film. A high optical transparency of ≈78.0% (≈0.65% variation) is measured across a 25 cm² area for a 10 μm thick dielectric. The dielectric property of the composite is also consistent, with a measured areal capacitance variation of <8% across 64 printed capacitors. The formulation represents an optically transparent, flexible thin‐film, with enhanced dielectric constant for printed electronics.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Growth of Topological Insulator Bi2Se3 Thin Films on SrTiO3 with Large Tunability in Chemical Potential

The growth of high quality, gate‐tunable topological insulator Bi₂Se₃ thin films on SrTiO₃ substrates by molecular beam epitaxy is reported in this paper. The optimized substrate preparation procedures are critical for obtaining undoped Bi₂Se₃ thin films with sufficiently low carrier densities while maintaining the strong dielectric strength of the substrates. The large tunability in chemical potential is manifested in the greatly enhanced longitudinal resistivity and the reversal of the sign of the Hall resistivity at negative back‐gate voltages. These thin films provide a convenient basis for fabrication of hybrid devices consisting of gate‐tunable topological insulators and other materials such as a superconductor and a ferromagnet.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Solution‐Processed HafSOx and ZircSOx Inorganic Thin‐Film Dielectrics and Nanolaminates

New thin‐film dielectrics and nanolaminates have been synthesized via aqueous‐solution deposition of Hf and Zr sulfates, where facile gelation and vitrification of the precursor solution have been achieved without organic additives. X‐ray reflectivity, imaging, and metal‐insulator‐metal capacitor performance reveal that smooth, atomically dense films are readily produced by spin coating and modest thermal treatment (T < 325 °C). Dielectric characteristics include permittivities covering the range of 9–12 with breakdown fields up to 6 MV cm^–1. Performance as gate dielectrics is demonstrated in field‐effect transistors exhibiting small gate‐leakage currents and qualitatively ideal device performance. The low‐temperature processing, uniformity, and pore‐free nature of the films have also allowed construction of unique, high‐resolution nanolaminates exhibiting individual layers as thin as 3 nm.     

Preparation of device-quality SiO2 thin films by remote plasma-enhanced chemical vapour deposition (PECVD): Applications in metal-oxide-semiconductor (MOS) devices

This review focuses on the evolution of a low-temperature remote plasma-assisted deposition process that has yielded device-quality SiO₂ and SiO₂-Si₃N₄ alloy thin films as defined by their performance in metal-oxide-semiconductor (MOS) devices. The evaluation of the dielectric films with respect to both the plasma deposition process and the device performance cannot be separated from (i) the pre-deposition surface cleaning of the crystalline silicon (c-Si) substrates and (ii) the way in which the Si-SiO₂ interface is formed. As a consequence, we show that this approach for using plasma-deposited SiO₂ films as gate dielectrics must of necessity combine (i) the final cleaning of the Si surface, (ii) the formation of the Si-SO₂ interface and (iii) the deposition of the gate oxide or nitrided oxide film into an in-situ integrated processing sequence.     

Anisotropy of Charge Transport in a Uniaxially Aligned and Chain‐Extended,High‐Mobility,Conjugated Polymer Semiconductor

Charge transport in the ribbon phase of poly(2,5‐bis(3‐alkylthiophen‐2‐yl)thieno[3,2‐b]thiophene) (PBTTT)—one of the most highly ordered, chain‐extended crystalline microstructures available in a conjugated polymer semiconductor—is studied. Ribbon‐phase PBTTT has previously been found not to exhibit high carrier mobilities, but it is shown here that field‐effect mobilities depend strongly on the device architecture and active interface. When devices are constructed such that the ribbon‐phase films are in contact with either a polymer gate dielectric or an SiO₂ gate dielectric modified by a hydrophobic, self‐assembled monolayer, high mobilities of up to 0.4 cm² V^?1 s^?1 can be achieved, which is comparable to those observed previously in terrace‐phase PBTTT. In uniaxially aligned, zone‐cast films of ribbon‐phase PBTTT the mobility anisotropy is measured for transport both parallel and perpendicular to the polymer chain direction. The mobility anisotropy is relatively small, with the mobility along the polymer chain direction being higher by a factor of 3–5, consistent with the grain size encountered in the two transport directions.     

Tunable Crystal Nanostructures of Pentacene Thin Films on Gate Dielectrics Possessing Surface‐Order Control

To enhance the electrical performance of pentacene‐based field‐effect transistors (FETs) by tuning the surface‐induced ordering of pentacene crystals, we controlled the physical interactions at the semiconductor/gate dielectric (SiO₂) interface by inserting a hydrophobic self‐assembled monolayer (SAM, CH₃‐terminal) of organoalkyl‐silanes with an alkyl chain length of C8, C12, C16, or C18, as a complementary interlayer. We found that, depending on the physical structure of the dielectric surfaces, which was found to depend on the alkyl chain length of the SAM (ordered for C18 and disordered for C8), the pentacene nano‐layers in contact with the SAM could adopt two competing crystalline phases—a “thin‐film phase” and “bulk phase” – which affected the π‐conjugated nanostructures in the ultrathin and subsequently thick films. The field‐effect mobilities of the FET devices varied by more than a factor of 3 depending on the alkyl chain length of the SAM, reaching values as high as 0.6 cm² V^?1 s^?1 for the disordered SAM‐treated SiO₂ gate‐dielectric. This remarkable change in device performance can be explained by the production of well π‐conjugated and large crystal grains in the pentacene nanolayers formed on a disordered SAM surface. The enhanced electrical properties observed for systems with disordered SAMs can be attributed to the surfaces of these SAMs having fewer nucleation sites and a higher lateral diffusion rate of the first seeding pentacene molecules on the dielectric surfaces, due to the disordered and more mobile surface state of the short alkyl SAM.     

Electrical characteristics of very thin SiO2deposited at low substrate temperatures

Very thin (≲ 100-Å) films of SiO2have been deposited by a modified plasma-enhanced chemical-vapor deposition (PECVD) process at very low substrate temperatures (≲ 350°C). Low flow rates of reactive gases and a high flow of inert carrier gas were used to lower the deposition rate, ensuring improved dielectric properties and good control over film thickness. Measurements made on MOS capacitors of current-voltage characteristics, electrical breakdown, interface trap density, and mobile ion drift indicate that these very thin PECVD films are approaching thermally grown SiO2in quality and may be suitable as gate dielectrics in device applications.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study n- and pMOS devices with 3.2–30 nm thick SiON or SiO₂ gate dielectrics and n⁺⁺ or p⁺⁺ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p⁺⁺ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n⁺⁺ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created.     

Role of ultrathin Al2O3 layer in organic/inorganic hybrid gate dielectrics for flexibility improvement of InGaZnO thin film transistors

We investigated flexible amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) on a polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and ultrathin Al₂O₃. IGZO TFTs were fabricated with hybrid PVP/Al₂O₃ gate dielectrics having Al₂O₃ layers of different nanoscale thicknesses, which were deposited by atomic layer deposition (ALD). The electrical characteristics of the TFTs with the organic/inorganic hybrid gate dielectrics were measured after cyclic bending up to 1,00,000 cycles at the bending radius of 10 mm. The ultrathin Al₂O₃ layer in the hybrid gate dielectrics improved the mechanical flexibility and protected the organic gate dielectric against damage during the sputter deposition of the IGZO layer. Finite elements method (FEM) simulations along with the structural characterization of the cyclically bent device showed the importance of optimizing the thickness of the Al₂O₃ layer in the hybrid gate dielectrics to obtain mechanically stable and flexible a-IGZO TFTs.     

High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors

High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.     

Electrical properties of Ru and RuO2 gate electrodes for Si-PMOSFET with ZrO2 and Zr-silicate dielectrics

In this work, we have studied the electrical and thermal stability of Ru and RuO₂ electrodes on ZrO₂ and Zr-silicate dielectrics. Very low resistivity Ru and rutile stoichiometric RuO₂ films, deposited by reactive sputtering, were evaluated as gate electrodes on ultrathin ZrO₂ and Zr-silicate (∼2.7 nm) films for Si-PMOS devices. Thermal and chemical stability of the electrodes were studied at annealing temperatures up to 800°C in N₂ followed by a forming gas anneal. X-ray diffraction (XRD), transmission electron microscopy (TEM), and x-ray photoelectron spectroscopy (XPS) methods were used to study grain structure and interface reactions. Electrical properties were evaluated using MOS capacitors. The role of oxygen in these dielectrics was studied by comparing equivalent oxide thickness (EOT) changes as a function of annealing temperature for capacitors with ZrO₂ and Zr-silicate dielectrics. For capacitors with Ru and RuO₂ gate electrodes on both ZrO₂ and Zr-silicate, excellent stability of EOT was detected. Flatband voltage and gate current as a function of annealing temperature were also studied. These studies indicate that Ru and RuO₂ are promising gate electrodes for P-MOSFETs.