基于RM型三变量通用逻辑门的查表设计

本文讨论了逻辑函数的RM展开与分类，给出了基于逻辑函数RM展开的三变量函数P分类表、接线顺序表以及P分类代表函数的接线方案。在此基础上提出了基于RM型三变量通用逻辑门的查表设计方法，并给出了具体设计实例。     

时序险象基本判据

本文利用几个定义和限制，得到了一外部激励ｘ，ｎ个状态变量电位异步时序电路的任一状态的一般逻辑表达式－特性方程、将此方程与状态表结合导出了产生时序险象时的状态变量数和稳定状态数所满足的条件；给出了对时序险象研究特别有用的基本判定法则。     

基于RTD的新型全加器设计

单双稳态转换逻辑单元(MOBILE)是基于共振隧穿二极管(RTD)电路的一个重要逻辑单元,非常适合阈值逻辑电路设计。由MOBILE可以构成阈值逻辑门(TG)和广义阈值逻辑门(GTG)等阈值逻辑电路。本文通过将三变量异或函数转化为较简单、理想的GTG输入输出函数形式,设计了由GTG构成的新型三变量异或门,并利用该三变量异或门设计了新型的全加器。通过HSPICE仿真和性能比较,该全加器不仅器件数量少,输出延时短,而且能达到较高的工作频率、更小的电路功耗与功耗-延迟积。     

时序险象基本判据

本文利用几个定义和限制,得到了一外部激励x,n个状态变量电位异步时序电路的任一状态的一般逻辑表达式特性方程.将此方程与状态表结合,导出了产生时序险象时的状态变量数和稳定状态数所满足的条件;给出了对时序险象研究特别有用的基本判定法则.     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

基于共振隧穿二极管的阈值逻辑单元电路设计

共振隧穿二极管作为较为成熟的纳米电子器件,已被广泛应用于高速低功耗电路。由于其具有负内阻特性,单一门电路的功能大大增加,减少了电路的复杂度。在阈值逻辑函数的硬件实现方面,共振隧穿器件也体现出显著的优势。结合谱技术,基于共振隧穿二极管,设计了可实现任意三变量阈值逻辑函数的阈值逻辑单元电路。该电路还可作为阈值逻辑网络中的基本单元,实现复杂的逻辑功能。通过HSPICE软件,仿真验证了所设计电路的正确性。     

m值“复合”逻辑函数的Chrestenson循环谱、自相关函数及应用

该文利用反演公式求得了m值“复合”逻辑函数的Chrestenson循环谱的计算公式，并由此得到了m值“复合”逻辑函数的自相关函数的计算公式，进而运用这两个公式，给出了m值“复合”逻辑函数具备平衡性、相关免疫性的条件，并对m值“复合”逻辑函数的自相关函数及其性质进行了分析；此外该文还得到有限个m值“复合”逻辑函数的非零线性和函数的Chrestenson循环谱的计算公式。     

复合卡诺图在多输出组合逻辑电路设计中的应用

为了使设计的多输出组合逻辑电路达到最简,运用复合卡诺图化简多输出函数,找出其各项的公共项,得到的表达式不一定是最简的,但是通过找公共项,使电路中尽量使用共用的逻辑门,从而减少电路整体的逻辑门,使电路简单。结果表明,利用复合卡诺图化简后设计出的电路更为简单。     

功能险象的简化快速算法研究

本文利用参与逻辑函数和逻辑函数余式的理论，得到了一第列重要的规律，使用导出的等效二变量逻辑余式状态变化过程对功能冒险精确定位，避免了繁琐沉得的计算，为数字电路和计算机奠定了基础。     

集成数据选择器实现组合逻辑函数技巧

用集成数据选择器可以实现任意组合逻辑函数,实现的方法有代数法和卡诺图法,当逻辑函数变量数较多时,代数法求解过程繁琐,而卡诺图法求解过程较简单。本文给出了用卡诺图法实现任意组合逻辑函数（含约束项和不含约束项两种情况）的方法,教学实践证明,这方法学生容易接受和理解,有较好的教学效果。     

Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine

The goal of this research is to enable the actual building of parallel machines. The example chosen in this paper is a heterogeneous parallel machine with an intrinsic asynchronous behavior. An asynchronous router fully supports such a logical asynchronism. However, every parallel processor would exhibit asynchronism similar enough to warrant the study of a general methodology. The main part of the paper deals with an original method that ensures a hazard-free self-timed design assuming the worst conditions for robustness. Hazards are classified under three types. On top of logic hazards that resort to implementation, equation hazards are eliminated by an optimal covering. A new variable labelled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The method was fruitfully applied to the VLSI CMOS implementation of the above-mentioned router. Peculiar fully customized cells were designed. Circuit-measured performances as well as some machine inner-communication performances are presented.     

DCNA Higher Level Protocols

This paper explains a philosophy for modeling the higher level communication functions into a network architecture for heterogeneous computer networks called Data Communication Network Architecture (DCNA), the logical structure of the architecture, and several protocols based on it. To specify higher level protocols among computers of different types, DCNA defines a logical model of a computer network consisting of three submodels: the basic model, the logical network model, and the virtual network model. The basic model represents a logical view of the network resources, e.g., processing power, files, data bases, I/O devices, and a layered structure for the basic mechanisms for accessing such resources, which incorporate the concept of sublevels as well as levels. The logical network model describes the mechanisms for unified management of network resources. The virtual network model describes the mechanisms for using network resources. The. common use of network resources, by several sets of interrelated applications is made easier by treating the logical network and the virtual network separately. These models form the basis for the stipulation of higher level protocols, such as network management protocols, message transfer protocols, virtual terminal protocols, and virtual file system protocols.     

A structural approach of pattern recognition

After defining the usual terms, a Pattern Recognition problem is stated as the linking of a representation to an interpretation. A basic knowledge is (dis)similarity measures. It is shown how the structure of the interpretation space conditions the law on this measure: usually both are homomorphic. We review the application of these ideas to clustering, hierarchies and first level recognitions, to statistical PR, to the fuzzy set approach, to information measures and even to logical statement interpretations.     

GSM的测试要求

本文根据GSM系统的结构、多址方式、物理和逻辑信道及其业务,提出了在开放系统互连模型的最低三层上的GSM测试要求和对移动台、基站的测试要求。     

一种改进的加权关联规则挖掘算法

基于经典Apriori算法的加权关联规则挖掘算法New-Apriori存在3个问题,需要多次扫描数据库,权值定义不合理和权值的引入导致Apriori基本性质不再成立。为了解决这些问题,采用将矩阵和加权关联规则算法相结合的方法,该改进算法具有只需要扫描一次数据库,权值的定义既考虑到了权重大的项目,也没有忽略频繁出现而权重小的项目,并引入K-项支持期望作为减枝的依据的特点。     

Tutorial: Petri nets as a graphical description medium for manyreliability scenarios

One of the basic problems of dependability modeling is the adequate abstraction of real-world technological problems to the principle terms of reliability/safety scenarios. This concerns primarily the definition of components and of faults on different system levels. Given these terms the rest of any modeling needs basic logical operations, mostly AND and OR, and delays, and often some counting (of time or events). All of these basic operations are offered by a fairly simple kind of Petri net (PN), i.e., timed stochastic Petri nets, allowing also for the modeling of immediate activities and of such with a deterministic delay. In this half-tutorial paper it is shown how such Petri nets modeling, i.e., the construction of the relevant nets, works in practice. No math will be needed for that. Several typical engineering virtues are needed; primarily imagination as to how to (i) find simple solutions, since often nonelegant solutions can be correct too, (ii) compose larger PN from elementary building blocks, and (iii) the ability to model the real world by interpreting the so-called tokens of a PN intelligently in different places of one and the same PN. In the appendix it is shown how the PN can also help in the analytical analysis of nonrepairable systems. In that context they are superior to state graphs since they show state durations explicitly     

Optimized reversible arithmetic logic units

Arithmetic Logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.     

基于交通故障报警系统的组合逻辑电路的设计

用数字信号完成对数字量进行算术运算和逻辑运算的电路称为数字电路,可以分为组合逻辑电路和时序逻辑电路两大类.其中,组合逻辑电路是由最基本的逻辑门电路组合而成.文章以交通故障报警系统为例介绍了三种设计方案,以便学生熟悉常见组合逻辑电路的特点及应用.     

多值逻辑基本运算的神经网络实现

多层感知器神经网络是典型的人工神经网络模型。算后，将其推广到多值逻辑。根据感知器神经元的分类特点，系统中的基本运算，从而也实现了任意三值逻辑函数。本文在分析二值感知器神经网络实现二值数字逻辑运采用三层前向稳健感知器神经网络实现了三值格代数。