Current-Mode High-Accuracy High-Precision CMOS Amplifiers

In low-voltage, deep sub- mum analog CMOS circuits, the accuracy and precision can be limited by the finite gain as well as by the input offset and 1/f noise voltages of opamps. Here, we show how to design high-accuracy high-precision CMOS amplifiers by properly applying dynamic element matching to a second-generation current conveyor (CCII); if all of the critical, nominally identical transistor pairs are dynamically matched, the resulting amplifier has low residual input offset and noise voltages. When compared with chopper or traditional dynamic element-matching amplifiers, the proposed approach alleviates the tradeoff between output swing and output resistance and is more robust against the finite opamp gain. Transistor-level simulations confirm theoretical results.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

Design, Implementation, and Testing of Miniaturized Electromagnetic Bandgap Structures for Broadband Switching Noise Mitigation in High-Speed PCBs

In recent years, advances in CMOS technology, resulted in devices with higher switching speeds, lower power supply voltages, and higher package densities. Lowering the power supply voltages and hence the power consumption of a single transistor, has been possible due to the fact that these new technologies are able to provide smaller and faster transistors with lower threshold levels. The benefits associated with lowering the threshold levels of the transistors used in a given device comes at a high-price, specifically the decrease of immunity of such device to noise and fluctuations of the power supply voltages. This paper covers the concept of embedding electromagnetic bandgap (EBG) structures in conventional power distribution networks in order to increase the immunity of the circuits that feed from such networks to noise and voltage fluctuations. Underlying theories of embedded EBG (EEBG) structures and design methodologies are presented. Finally, in order to provide immunity to high-bandwidth noise, voltage fluctuations and radiation, new EEBG configurations, topologies and miniaturized structures with ultra wide-bandwidth are introduced and their efficacy is demonstrated     

A monolithically integrated three-axis accelerometer using CMOScompatible stress-sensitive differential amplifiers

In this paper, the development of a bulk-micromachined CMOS integrated three-axis accelerometer which includes analog signal conditioning circuits is presented. The accelerometer was designed to simplify the signal processing tasks by incorporating a set of circuits for three-axis signal conditioning. This approach resulted in a 25% reduction of the circuit area. Stress-sensitive differential amplifiers (SSDAs) have been used as signal transducers, because they can be conveniently formed in a small area. The sensitivity and resolution of the fabricated devices realized in 8×8 mm² die area were 192 mV/g and 0.024 g for Z-axis acceleration, and 23 mV/g and 0.23 g for X and Y axis acceleration, respectively. The electrical noise component in the analog CMOS circuits was reduced by using a chopper stabilization technique. It was observed that there is a proper chopping clock frequency range to maximize the noise reduction effect. The noise of the SSDA was found to be related with the characteristics of CMOS differential amplifiers used. Typical temperature coefficient of sensitivity was about -2000 ppm/°C, which could be reduced to -320 ppm/°C or less by selecting a proper bias condition     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Redox Memristors with Volatile Threshold Switching Behavior for Neuromorphic Computing

The spiking neural network(SNN), closely inspired by the human brain, is one of the most powerful platforms to enable highly efficient, low cost, and robust neuromorphic computations in hardware using traditional or emerging electron devices within an integrated system. In the hardware implementation, the building of artificial spiking neurons is fundamental for constructing the whole system. However, with the slowing down of Moore’s Law,the traditional complementary metal-oxide-semiconductor(CM...     

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.     

Designing low-power circuits: practical recipes

The growing market of mobile, battery-powered electronic systems (e.g., cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. More generally, as density, size, and complexity of the chips continue to increase, the difficulty in providing adequate cooling might either add significant cost or limit the functionality of the computing systems which make use of those integrated circuits. In the past ten years, several techniques, methodologies and tools for designing low-power circuits have been presented in the scientific literature. However only a few of them have found their way in current design flows. The purpose of this paper is to summarize, mainly by way of examples, what in our experience are the most trustful approaches to low-power design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power design; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint. We will focus solely on digital circuits, and we will restrict our attention to CMOS devices, this technology being the most widely adopted in current VLSI systems     

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design

Exponential increase in leakage power has emerged as a major barrier to technology scaling. Existing circuit techniques for leakage reduction either suffer from reduced effectiveness at nanometer technologies or affect performance and gate-oxide reliability. In this paper, we propose application of a specific carbon nanotube (CNT)-based nano-electromechanical switch as a leakage-control structure in logic and memory circuits. In case of memory circuits, we demonstrate that the proposed hybridization can be employed to reduce both cell leakage and bitline leakage, thereby improving the read noise margin as well. Due to the unique electromechanical properties of CNTs, these switches have high current-carrying capacity, extremely low leakage current, and low operating voltages. Moreover, they can act as nonvolatile memory elements, which can be exploited for data retention of important registers and latches during power down. Simulation results for a set of benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing multi-threshold CMOS technique. In memory circuits, simulations show reduction in standby leakage and reduction in bitline leakage compared with the best existing techniques.     

Low-power CMOS digital design with dual embedded adaptive powersupplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design     

A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

A wired-AND current-mode logic (WCML) circuit techniquein CMOS technology for low-voltage and high-speed VLSI circuitsis proposed, and a WCML cell library is developed using standard0.8 micron CMOS process. The proposed WCML technique appliesthe analog circuit design methodologies to the digital circuitdesign. The input and output logic signals are represented bycurrent quantities. The supply current of the logic circuitis adjustable for the required logic speed and the switchingnoise level. The noise is reduced on the power supply lines andin the substrate by the current-steering technique and by thesmooth swing of the reduced node potentials. Precise analogcircuits and fast digital circuits can be integrated on the samesilicon substrate by using the low noise property of the WCML.It is shown by the simulations that at low supply voltages, theWCML is faster and generates less switching noise when comparedto the static-CMOS logic. At high speeds, the power dissipationof the WCML is less than that of the static-CMOS logic.     

CMOS wireless transceivers: the new wave

A new generation of wireless transceivers is being intergrated into CMOS IC technology, which so far has been used mainly to realize digital and mixed analog-digital baseband circuits. This article reviews some of the RF CMOS circuit design techniques, and shows how an understanding of the strengths and weaknesses of these circuits influences choice of radio architecture. The CMOS approach to radio design calls for the elimination of discrete components in favor of high levels of on-chip integration which freely use translators and mix analog and digital functionality; in these respects, it departs from traditional RF circuit practices. Successful wireless devices of the future will require that radio system design evolve around these new trends in RF integration     

Noise in digital dynamic CMOS circuits

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits     

Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

In this paper, we present an analytical modeling methodology for fully integrated inductively-degenerated CMOS narrow-band cascode Low Noise Amplifiers (LNA) that captures short channel transistor effects to enable rapid design space exploration in current and future process technologies. The modeling methodology captures the impact of parasitics on passive components, ESD-protection structures, and devices to accurately predict both impedance matching and noise figure. Our modeling is suitable for numerical optimization and fully automated synthesis for LNAs. The results indicate that the methodology models ESD-protected LNA circuits with 47.9% better accuracy in noise figure when compared with several current analytical modeling techniques with four orders of magnitude improvement in simulation time over circuit-level simulation. Given its speed and accuracy, the analytical modeling methodology is well-suited for design space exploration.     

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.     

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

On gate level power optimization using dual-supply voltages

In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of stacks. Based on this strategy, the power reduction is translated into the polynomial-time-solvable maximal-weighted-independent-set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dual-supply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a “constrained F-M” algorithm to minimize the number of level converters. We have implemented our approach under an SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted “optimum” supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by the gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimization     

An efficient current-based logic cell model for crosstalk delay analysis

Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.