Designing Nanoscale Logic Circuits Based on Markov Random Fields

As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future is retaining high reliability in the presence of faulty devices and noise. Probabilistic computing offers one possible approach. In this paper we describe our approach for mapping circuits onto CMOS using principles of probabilistic computation. In particular, we demonstrate how Markov random field elements may be built in CMOS and used to design combinational circuits running at ultra low supply voltages. We show that with our new design strategy, circuits can operate in highly noisy conditions and provide superior noise immunity, at reduced power dissipation. If extended to more complex circuits, our approach could lead to a paradigm shift in computing architecture without abandoning the dominant silicon CMOS technology.     

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.     

Nanowire Crossbar Logic and Standard Cell-Based Integration

Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. However, it is still unclear whether or how they can be competitive in implementing logic circuits, as compared to their MOSFET counterparts. We analyze nanowire crossbars in area, speed, and power, in comparison with their MOSFET counterparts. We show nanowire crossbars do not scale well in terms of logic density and speed. To achieve performance close to their MOSFET counterparts, crossbar circuits need faster field-effect transistors (FETs) to compensate the high resistance of nanowires. Motivated by the analysis and comparative study, we propose a crossbar cells design based on judicious use of silicon nanowires. The crossbar cell is compatible with the conventional MOSFET fabrication and design methodologies, in particular, standard cell-based integrated circuit design. We evaluate logic circuits synthesized with crossbar cells and MOSFET cells based on the MCNC91 benchmark. The results show that crossbar cells can provide a density advantage of more than four times over the traditional MOSFET circuits with the same process technology, while achieving close performance and consuming less than one third power.      

Individual Confinement of Block Copolymer Microdomains in Nanoscale Crossbar Templates

Highly ordered pattern formation of block copolymers (BCPs) within nanoscale templates is of great interest for generating diverse ordered nanostructures. Here, introduced is a combined methodology of nanotransfer printing (nTP) and BCP self‐assembly to guide the formation of spherical nanodots within a printed crossbar nanotemplate. By successfully accommodating poly(styrene‐b‐dimethylsiloxane) (PS‐b‐PDMS) BCPs in the guiding metallic crossbar nanotemplate (≈30 × 30 nm²), a well‐organized array of single‐domain PDMS spheres (≈10 nm) with a square symmetry is successfully obtained in an extremely short annealing time (<5 s). The self‐consistent field theory simulation results theoretically explain the spontaneous one‐to‐one accommodation of PDMS spheres in the confined area of the crossbar template. This approach can potentially be extended to the many other BCP materials and morphologies to diversify the geometry of self‐assembled BCP and/or transfer‐printed nanopatterns for various types of nanodevice applications.     

Reliability Analysis of Logic Circuits

An efficient algorithm is presented for computing the reliability matrix of a logic network whose components are characterized by a known probability of malfunctioning. Using the concept of path sensitizing, a graphical representation of error propagation is derived. Through the computation of Boolean path functions, the information provided by these graphs is put into a malfunction table from which the matrix entries are directly computed. The method not only offers computational efficiency but also provides further physical insight into the reliability problem.     

逻辑电路神经网络模型

本文采用Hopfiold神经网络模型,从基本逻辑器件的真值表出发,建立其能量约束方程组,利用线性方程组理论推导出逻辑器件神经网络模型存在的充分必要条件,并由此得到基本逻辑门神经网络参数的一般表达式.     

组合逻辑多故障诊断

通过对布尔差分法的剖析,得到了组合电路单固定故障测试生成的简化方法。该方法不必进行异或运算,只须求解恒等式就能得到组合逻辑电路的８测试矢量。多故障的测试码产生可以对高阶布差分经过变换,转化为一阶布尔差分来处理,从而极大地减少了多故障测试生成的计算工作量。     

Adiabatic Logic Circuits: A Review

The current status of research and development in the field of adiabatic electronic devices for the production of information is reviewed. The adiabatic property means that the power supply regains most of the energy expended on computing. A design philosophy of universal adiabatic logic gates is framed. The gates are categorized according to adiabatic rank, the principle of operation, the method used to satisfy the thermal-equilibrium conditions, the information-storage technique, and the mode of operation. For adiabatic-gate drivers, existing design concepts are categorized and described. Promising avenues of development are outlined.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficient PAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficientPAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变     

三值GaAs逻辑级电路的研究

本文首先讨论了ＧａＡｓＦＥＴ对三值信号的处理过程,对二值ＧａＡｓ电路的输出级等效电路与基于已提出的电路结构的多值ＧａＡｓ电路的输出级的等效电路进行了分析,并分析了该多值ＧａＡｓ电路结构的缺陷及其产生缺陷根源。     

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

Fault-Tolerant System Using 3-Value Logic Circuits

A ternary decision circuit implemented in CMOS technology is proposed. It can be used in a duplex binary fault-tolerant system to replace both the matcher and the switch circuit. The resultant system is simpler than the conventional one. The reliable design of the ternary decision circuit is discussed in detail. A duplex 2-of-3-value fault-tolerant system can be formed by two 2-of-3-value processors and a TDC. This system is more powerful than a duplex binary system since it can provide automatic error correcting function for certain faults. All single faults can be divided into self-checked faults and secure faults. For any self-checked faults, the TDC is self-testing, strongly fault secure, and totally self-checking. For any secure faults, the TDC is strongly fault secure.     

Defect-tolerant hierarchical sorting networks for wafer-scaleintegration

A novel hierarchical defect-tolerant sorting network that meets application requirements and area-time complexity constraints is presented. It is very regular in structure and hence easier to reconfigure than any existing sorting network with the same time complexity. Redundancy is provided at every level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the defective cells with spare cells at the lowest level first, and reconfiguration goes to the next higher level if there is not enough redundancy at the current level. These redundant cells can be used for single error correction at run time. Simulations demonstrate that significant yield improvements over other approaches can be achieved     

具有反馈结构的PAL-2NF电路

在分析PAL - 2 N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL - 2 NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL - 2 NF电路的设计方法,并在不同时钟频率下用1 .2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL - 2 NF反相器/缓冲器电路在功率时钟频率1 0 MHz时都比相应的PAL - 2 N电路节省93%以上的功耗,在4 0 0 MHz时功耗节省也可达4 0 % .由于几乎完全消除了输出端的悬空现象和逻辑0的“第三态”现象,PAL - 2 NF电路可以工作于更高的时钟频率和更低的输出波形畸变     

Building Functional Memories and Logic Circuits with 2D Boron Nitride

The fast development of synthesis routes and preparation technology of 2D materials has motivated a rapid growth in the micro- and nanoelectronic memory devices, which gives rise to the breakthroughs in the semiconductor research area. Hexagon boron nitride (h-BN) with excellent chemical, mechanical, and optical properties has been proven to have potential in overcoming the scaling limit to nanometer, and even sub-nanometer lengths to replace the use of thick and stiff blocking dielectrics in two-terminal or three-terminal devices. The use of atomically thin h-BN or h-BN van der Waals heterostructures (vdWhs) can improve the reliability, capability, and functionality of memory devices. This is an encouraging strategy toward high-density on-chip integrated circuits, which has recently earned considerable interest. While the research in h-BN material properties and characterization is comprehensively verified, specified mechanisms of resistive switching have not been analyzed in-depth. Moreover, recent concern about novel structure design and expanding applications in electronics, optoelectronics, and spintronics has arisen. In this review, recent progress in h-BN memories with volatile or nonvolatile properties is presented, expanding the memories to functional applications, and further challenges of the development of h-BN-based memories and logic circuits are discussed.     

具有反馈结构的PAL-2NF电路

在分析PAL-2N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL-2NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL-2NF电路的设计方法,并在不同时钟频率下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL-2NF反相器/缓冲器电路在功率时钟频率10MHz时都比相应的PAL-2N电路节省93%以上的功耗,在400MHz时功耗节省也可达40%.由于几乎完全消除了输出端的悬空现象和逻辑0的"第三态"现象,PAL-2NF电路可以工作于更高的时钟频率和更低的输出波形畸变.     

Integrated Conditioned OR and Inhibited OR Logic Circuits

High-speed logic circuits capable of subnanosecond operation are described. The circuits may be constructed using monolithic transistor circuits and attached tunnel diodes, or entirely in hybrid integrated form. A capacitance isolation technique allowing the use of conventional monolithic current mode logic (CML) circuits in conjuction with tunnel diodes is also presented. This results in considerably increased speed and logic flexibility. With this approach, the potential low cost of monolithic circuits of large production volume and the high-speed capability of the tunnel diodes are both retained. Using commercially available tunnel diodes and monolithic circuits, average propagation delays of under 0.4 ns were achieved in an operating system. This represents about an order of magnitude improvement over speeds obtainable with monolithic circuits alone for an important class of logic functions. Good noise immunity is obtained since the tunnel diodes perform only the analog threshold OR operation. The described CONDITIONED OR and INHIBITED OR circuit family is logically complete; however, it is particularly suited for iterative logic. The circuit operation and characteristics are discussed in detail. Examples of their use are also given.