一种适用于内嵌时钟串行链路的5Gbps小面积CDR

本文提出了一种支持多标准的具有系数可调的均衡器和宽跟踪能力的时钟数据恢复电路。基于对系统参数和一阶 bang-bang 时钟数据恢复电路的环路特性分析,推导出电路设计参数。考虑到抖动性能,追踪能力以及芯片面积,文中采用了一阶数字滤波器和6-bit DAC以及高线性度的相位插值器实现了高相位调整精度和小面积的时钟恢复电路,同时该结构实现了±2200ppm的频偏跟踪能力,使得该结构适用于不同源的高速串行传输系统,尤其是内嵌时钟结构。该设计已经在55nm CMOS工艺上流片验证,测试结果显示符合误码率的要求以及抖动容忍规范。该测试芯片整体面积是0.19mm2,其中时钟恢复电路只占0.0486mm2 而且该电路工作在5Gbps,供电电压为1.2V时,只消耗30mW。     

A low-noise fast-lock phase-locked loop with adaptive bandwidthcontrol

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range     

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered.     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.     

基于DDS 与PLL 的C 波段宽带线性扫频源

利用直接数字频率合成(DDS)和锁相环(PLL)技术相结合的混合频率合成方案,研制了一种C波段宽带、高频率分辨率、快速线性扫频的频率源。为了给PLL 提供低相位噪声的宽带扫频参考信号,选用ADI 的DDS芯片AD9914,并利用阶跃恢复二极管(SRD)高次倍频电路结合二倍频器产生高达3400 MHz 的时钟信号。通过上位机配置AD9914 内部频率调谐字和数字斜坡发生器,产生512.5-987.5MHz 的扫频参考信号,其频率分辨率可精细到赫兹量级。选用低附加噪声的鉴相器和宽带VCO 芯片设计C 波段锁相源,在宽带工作频率范围内对DDS 扫频信号进行快速跟踪,并有效抑制杂散信号。实测结果表明,该扫频源工作频率为4. 1- 7. 9 GHz,在频率分辨率配置为0. 38 MHz 时,单向扫频周期为1 ms,扫频线性度为1. 58×10-6 。单频点输出时相位噪声优于-114 dBc/ Hz@ 10 kHz和-119 dBc/ Hz@ 100 kHz,杂散抑制优于69 dBc。     

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction ($-$19 dB to the non-SSC situation) and a small core area of 0.25 mm $^{2}$ in 0.13- $mu$m CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm $^{2}$. Moreover, it achieved good jitter tolerance (flat 0.8 UI at $> $1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.      

用步进锁相扫描技术改进VCO线性及调频带宽稳定性

选用HMC703LP4E小数频率综合器与专门设计的有源环路滤波器和商用VCO构成了步进扫描数字锁相环,改进了调频连续波的调频带宽稳定性和调频线性度。对设计的电路进行了制作和测试,实验结果表明在-30^+70℃温度范围内,调频信号的稳定度达到了1×10^-6,调频线性度接近于1.0,相位噪声为-90 dBc/Hz/10 kHz。     

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies     

一种具有相位噪声跟踪补偿的全数字锁相环频率合成器

为了实现频率合成器中的相位噪声跟踪补偿和降低全数字锁相环的复杂性,本文提出了一种新的基于全数字锁相环的频率合成器。它采用了一种低复杂度的数字鉴频鉴相器和非线性相位/频率判决电路以及数控振荡器,从而显著降低了硬件复杂性。同时结构中采用的非线性相位和频率判决电路能够很好地实现噪声跟踪和快速的相位/频率捕获,数控振荡器能够获得高的频率分辨率(大约6kHz)和大的线性频率调谐范围。通过采用90nm CMOS工艺制造的ADPLL实验结果表明,本文所提出的基于全数字锁相环的频率合成器能够实现从100kHz到6MHz的可控环路带宽和相当好的带内相位噪声跟踪性能。     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 $mu{hbox{s}}$. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under $-$ 75 dBc. The phase noise at 400 kHz and 3 MHz are $-$115.6 dBc/Hz and $-$134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 $mu$ m CMOS process, and occupies an active area of 0.85 ${hbox{mm}}^{2}$ and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.      

一种扩展载波环频率捕获范围的方法

在MPSK数字载波恢复中,可以通过锁频锁相环捕获大范围频率偏移。低信噪比下,锁相环的频率捕获范围较小,而工程中锁频环剩余频偏通常较大,因而需要扩展锁相环的频率捕获范围。描述了频差估计以及COSTAS环中相位检测技术的实现方法,分析了COSTAS环的相位检测特性,并根据这种算法的鉴相特性提出了一种扩展频率捕获范围的载波恢复方法。以QPSK为例,通过MATLAB仿真了这种技术在低信噪比情况下对频率偏移的检测与跟踪性能,仿真结果表明,提出的方法适合低信噪比下大范围的频率捕获。     

A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter

A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

An interpolating clock synthesizer

A digital alternative to analog phase-locked loop (PLL)-based clock generators for microprocessors, denoted an interpolating clock synthesizer (ICS), is described. Using ROM-based digital waveform synthesis, the ICS implements a wide range of frequency multiples having the form P/Q, where P and Q are integers. The ICS outputs two synthesized clocks, one for the I/O interface having a 1/1 frequency multiple and one for the core having one of eight dynamically-selectable frequency multiples (1/1, 3/2, 5/3, 2/1, 5/2, 3/1, 15/4, and 5/1). The ICS uses a synchronous delay line as a coarse (T_p/30) timing reference, while through digital delay interpolation it achieves a fine delay resolution of 0.04 ns. Using a completely digital precision phase detector, the ICS achieves a DC skew of ±0.05 ns     

A $Delta{-}Sigma$ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A triangular-modulated spread-spectrum clock generator using a$Delta{-}Sigma$-modulated fractional-$N$ phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased $Delta{-}Sigma$ operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of $pm$0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies $950times850 {rm mu}{rm m}^{2}$ in 0.18-${rm mu}{rm m}$ CMOS process and consumes 36 mW.      

基于FPGA实现的一种新型数字锁相环

针对高频感应加热电源中用传统的模拟锁相环跟踪频率所存在的问题,提出一种非常适合于高频感应加热的新型的数字锁相环。使用FPGA内底层嵌入功能单元中的数字锁相环74HCT297,并添加少量的数字电路来实现。最后利用仿真波形验证该设计的合理性和有效性。整个设计负载范围宽、锁相时间短,现已成功应用于100 kHz/30 kW的感应加热电源中。     

A low-jitter 125-1250-MHz process-independent and ripple-poleless0.18-μm CMOS PLL based on a sample-reset loop filter

This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18-μm CMOS process. A sample-reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering pole, leading to a nearly 90° phase margin which minimizes input jitter peaking and transient locking overshoot. The PLL damping factor is made insensitive to process variations by making it dependent only upon a bandgap voltage and ratios of circuit elements. This ensures tracking between the natural frequency and the stabilizing zero. The PLL has a frequency range of 125-1250 MHz, frequency resolution better than 500 kHz, and rms jitter less than 0.9% of the oscillator period     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.