Prediction of interfacial delamination in stacked IC structures using combined experimental and simulation methods

Interfacial delamination is an often-observed failure mode in multi-layered IC packaging structures, which will not only influence the yield of wafer processes, but also have direct impact on the packaging reliability. The difference in coefficient of thermal expansion, together with thermal and thermal–mechanical loading are the main driving forces for interfacial delamination. First of all, this type of delamination is considered as a mixed mode of failure at the material interfaces. Hence, at least two stress components are needed to predict its occurrence. However, due to the singular stress field at the interface, one could hardly obtain the correct stresses at the interface. Therefore, a combined experimental–numerical method is used to investigate the initiation and propagation of the interface delamination. The purpose of the experimental shear and tensile tests is to measure the critical loads, at which delamination initiates. Then, a Finite Element (FE) model is constructed to convert the critical load into critical failure data for further numerical investigation. The FE model is so constructed that it reproduces the geometrical configurations of the tests. Due to the singular stress distribution at the interface, the calculated local stresses will be both mesh and residual-stiffness dependent. The influences of the FE parameters on the interface stresses are studied. After that, a progressive failure approach is, in combination with a group of failure criteria and the estimated local critical stresses, applied to predict the initiation and propagation of the delamination between epoxy mould compound and the passivation layer in the Integrated Circuit (IC) for three different package structures. The present method and the obtained results are valuable to determine design rules for IC packaging structures.     

Fatigue life prediction of Package-on-Package stacking assembly under random vibration loading

This paper presents a general methodology to predict the fatigue life of the Package-on-Package (PoP) under random vibration loading by means of vibration tests and finite element (FE) simulation. The behavior of the critical solder joints of the PoP under vibration loading was accurately described by FE model using ANSYS software and confirmed by modal analysis and linear sweep tests. The stress-life (S-N) curve of the PoP solder joints was obtained by the sinusoidal fatigue vibration tests and FE simulations to characterize the fatigue properties of the PoP under vibration. The comparison of the S-N curves of the SAC305 solder joints in different structures indicates the S-N curve of the SAC305 solder joints depends on the package structure. With the same fatigue cycles, the stress levels for the current 3D package is the smallest compared with the other 2D package due to the stacked structure of the PoP. Spectrum analysis for the random vibration tests was performed by the FE simulations to acquire the stress response power spectral density (PSD) of the critical solder joint. A specific frequency domain approach based on the Palmgren-Miner's rule was established to predict the fatigue life of the PoP under random vibration. Results show that simulated fatigue life matches well with the random vibration test results, which implies that this approach could be a potential method for the predication of fatigue life of the 3D packaging under random vibration.     

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives. An erratum to this article is available at .     

Characterization of the Effect of Shape Memory Alloy on Solder Joint Strength Through Modeling and Testing

Currently some of the most common problems that surface mount technology encounters are warpage, delamination, and inelastic strain concentration accumulated in the solder joint during thermal cycling because of mismatch of thermal expansion coefficient between the package and chip side. Material as well as package structure are the critical issues with respect to these problems. The objective of this research is to investigate how shape memory alloy (SMA) applied in the under bump metallization (UBM) can affect solder joint reliability under thermal mechanical stress. Joint strength tests revealed the better strength of solder joints with SMA UBM after accelerated thermal cycling test. Finite element modeling as well as multilayer stress calculations revealed less strain accumulated in the solder and more stress concentrated in Si in the solder joint with SMA UBM. A mechanism by which the SMA accommodates most of the stress and strain caused by the mismatch of the thermal expansion coefficients was proposed to explain the reinforcement of the solder joint by the SMA UBM.     

The solder on rubber (SOR) interconnection design and its reliability assessment based on shear strength test and finite element analysis

A novel chip-on-metal structure of the advanced wafer level chip scale package (WLCSP) which has the capability of redistributing the electrical circuit is proposed in this study. In the WLCSP, the solder on rubber (SOR) design expands the chip area and also provides a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. By using the solder ball shear test, the stress/strain-released behavior in the SOR structure is investigated in this research. On the other hand, a three-dimensional nonlinear finite element (FE) model for the ball shear test is established to assist the design of the package. The force-displacement curves from the FE analysis are compared with the experimental results to demonstrate the accuracy of the simulation. Likewise, the issue from element mesh density is also discussed herein. The investigation reveals that the SOR structure could highly decrease the damage in solder bumps from the ball shear test. Furthermore, the transferred stress/strain in the interconnect near the contact pad could be diminished through a suitable layout of redistribution lines.     

Prediction of the epoxy moulding compound aging effect on package reliability

Most semi-conductor devices are encapsulated by epoxy moulding compound (EMC) material. Even after curing at the prescribed temperature and time in accordance with the supplier’s curing specifications often the product is not yet 100% fully cured. As a consequence, the curing process of a product continues much longer, leading to curing effects of the EMC during the lifetime of the package. In this paper, the effect of EMC curing during lifetime on package reliability is investigated. The visco-elastic mechanical properties of two commercial EMC materials are measured as a function of aging time. The resulting data is used to construct material models that are used in FE calculations. Aging effects on critical semi-conductor failure modes die cracking, compound cracking, wedge break, and delamination are addressed. Die and compound crack risks are predicted by common stress analysis. The risk of wedge break occurrence is investigated by detailed 3D modeling of the actual wires in the package using a global-local approach. Conclusions on delamination risks are made based on a parameter sensitivity analysis using a 3D cohesive zones approach to predict transient delamination. The package reliability study shows that the effect of EMC aging affects relevant failure modes in different ways.     

Study of the UBM to copper interface robustness of solder bumps in flip chip packages

Shear tests on SnAg solder bumps were performed with a reduced height to the surface for a high shear force on the under bump metallurgy (UBM) to redistribution layer (RDL) copper interface. By this the failure mechanism of UBM–RDL delamination after stress tests simulating several assembly reflows could be reproduced. A design of experiment was done with corner wafers at worst case conditions for topography and interface clean. TEM cross sections confirmed nano scale carbon residues in the interface when reducing the clean efficiency. This results in a mechanically weakened interface with a present electrical contact. The shear test with reduced height is a more severe test beyond the JEDEC test to verify the bump robustness. This is important when existing bump technologies are used for flip chip package solutions with increased solder reflow requirements.     

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

Influence of temperature, humidity, and defect location ondelamination in plastic IC packages

The modified J-integral and the stress intensity factor based on linear elastic fracture mechanics can be applied to predict the growth of interfacial delamination in integrated circuit (IC) packages. One of the key parameters required is the interfacial fracture toughness. This paper describes the measurement of the interfacial fracture toughness as a function of temperature and relative humidity using a three-point bending test. The interfacial fracture toughness was found to decrease with temperature and relative humidity. It is proposed that delaminations propagate from very small voids or defects present at the interface. The effect of the location of these interfacial defects or cracks on delamination was studied. The IC package evaluated in this paper was an 80-pin quad flat package with a 0.2 mm defect or crack at the edge or at the center of the interface. It was found that as the temperature of the package was increased, the stress intensity factor of the edge crack was higher than that of the center crack. However, whether the edge crack will propagate first as temperature is increased depends on the ratio of mode II interface toughness to that of the mode I interface toughness. For the package under investigation, it was established that when this ratio is less than 2.69 the edge crack would propagate first, otherwise the center crack would. For small defects, it was found that the water vapor pressure developed at the interface did not have a significant effect on the value of the crack-tip stress intensity factor     

Finite element modeling of electronic packages subjected to drop impact

As more electronic products become portable, many product manufacturers have started to pay more attention to the robustness of their products. Finite element (FE) simulation has become increasingly popular in the analysis of products subjected to impact loading. The need for details in a FE mesh is always balanced by considerations of simulation time and available computational resources. In this paper, three commonly used approaches to FE modeling of a ball grid array (BGA) package subjected to drop impact are evaluated. The first model comprises a detailed mesh of the printed circuit board (PCB), integrated circuit (IC) package and interconnecting solder balls using solid three-dimensional (3-D) elements. The degrees of freedom is reduced for the second mesh by using shell elements for the PCB and IC package while retaining the detailed mesh of the solder balls using solid 3-D elements. The third mesh is a further simplification of the second mesh whereby the solder balls are replaced by a single beam element each. The stresses within the solder balls are then obtained in a separate FE analysis of a detailed solder ball mesh using the displacement history of nodes around the beam elements from the previous analysis as inputs. Solder ball stresses from all three meshes were found to differ by as much as 40% although PCB deflection compared favorably.     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages

In this paper, using a recently developed solder fatigue model for wafer level-chip scale package (WL-CSP), we investigated the improvement on solder joint reliability for a 8-bump micro SMD package by enlarging the passivation layer opening at the solder–die interface. The motivation to enlarge the passivation opening is to reduce the severity of the stress concentration caused by the original design, and also to increase the contact area between the solder bump and aluminum bump pad. It was confirmed in the thermal shock test that with the new design, package fatigue life improved by more than 70%. To numerically predict this improvement represents a unique challenge to the modeling. This is because in order to capture the slightest geometrical difference on the order of a few microns between the two designs, the multiple-layer solder-die interface needs to be modeled using extremely fine mesh, while the overall dimensions of the package and the test board are on the order of millimeters. To bridge this tremendous gap in geometry, a single finite element model that incorporates all necessary geometrical details is deemed computationally prohibitive and impractical. In this paper, we applied a global–local modeling scheme that was also suggested by others [1, 2 and 3]. The global model contains the complete package with much simplified solder–die interface whereas the local model includes only one solder joint, but with detailed solder–die interface. Unlike most global–local models proposed by others, we included time-independent plasticity and temperature-dependent materials in the global model. This greatly improved model correlation accuracy with only moderate increase in run time. Energy-based solder fatigue model was used to correlate the inelastic strain energy with the package fatigue life. In an earlier study [4], we have found that Darveaux’s equations tended to be conservative when applied to the micro SMD, and hence new correlations based on curve-fitting the test data were derived. In this paper, we used the newly derived equation and achieved less than 20% error in N₅₀ life for both designs, which is on par with Darveaux’s equations when used for BGAs. The analysis also revealed two factors that may account for the life improvement. First, a slight decrease in inelastic energy dissipation after enlarging the passivation opening. Second, the shift of the crack initiation location which leads to longer crack growth length for the new design. The second factor was also independently confirmed by the failure analysis.     

Mechanical reliability in electronic packaging

The dramatic increase in the number of devices and functionality of the latest ultra large scale integration designs have resulted in increasing chip size. Concurrently, to achieve higher circuit board component densities, package dimensions have been shrinking. These two competing trends are leading to ever more rigorous requirements on the mechanical characteristics of the packaging technology. The dominant issue in component level reliability is delamination and cracks initiated at the interface between dissimilar materials. In board level reliability, solder joint reliability is a primary issue. This paper describes the methodology of prediction and the explanation for interfacial delamination, cracks at the top of the interfaces and the edge of corner, and also solder joint reliability. This paper furthermore presents the role of the chip backside contamination affecting interfacial delamination, the surface characterizations and an explanation of the interface chemistry, and the strength of solders with a variety of plating materials for Sn–Ag-based lead free solders.     

The effect of hygro-mechanical and thermo-mechanical stress on delamination of gold bump

The reliability of the FC–CSP (flip chip–chip scaled package) package with gold bump at the MRT (moisture resistance test) reflow temperature, was evaluated by using the finite element method. The moisture properties of EMC (epoxy molding compound) obtained from the test described in JEDEC standard, were used to characterize the local moisture concentration analysis by transient moisture diffusion, the hygro-mechanical analysis by CME, the vapor pressure analysis and the thermo-mechanical analysis by CTE mismatch. Also, after precondition, the package reliability under the reflow process was predicted, by comparing and integrating each factors, package swelling and stress due to by vapor pressure, as well as thermo-mechanical stress. Consequently, the result showed that the effects on hygro-mechanical stress and vapor pressure in a package could not be negligible, when it is compared with that of the thermo-mechanical stress by CTE mismatch, which is recognized as the main effect on the package crack under reflow temperature. The stress was concentrated at interface between gold bump and die, where most of delamination occurred.     

Influence of solder bump arrangements on molded IC encapsulation

This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different solder bump arrangements is considered in this study. In the FSI analysis, effects of solder bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and solder bumps are evaluated. The findings indicate that the full-array solder bump package encounters lower stress and deformation during encapsulation. The void formation of each solder bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.     

Development of a Novel Microimpact-Fatigue Tester and Its Application to Impact Reliability of Lead-Free Solder Joints

Drop-impact forces cause portable electronic devices to fail. Assessment of resistance against drop-impact force is required to predict life of an electronic package. Several methods have been used to evaluate impact-fatigue life and other advanced methods have been proposed. However, such conventional impact tests require excessive time and cost. In this paper, a novel micro-impact-fatigue tester is developed to overcome such drawbacks of conventional methods. A newly developed impact-fatigue apparatus directly applies impact force to solder joints and measures deformation of the solder joints. The impact-fatigue test apparatus consists of an electromagnetic actuator, an impact-pin, a load-cell, a displacement sensor, and a main frame. Electromagnetic actuator produces a repeatable impact force with a changeable amplitude and pulse duration. Impact-fatigue apparatus was used to test reliability of a lead-free solder (96.5Sn4.0Ag0.5Cu). An evaluation of impact-fatigue life was performed over a wide range of 1-10⁴ cycles with various applied forces ranging from 40 N to 110 N. Two failure modes were observed in a section inspection. First type of failure was a mixed mode failure, where a bulk solder failure and interface failure coincide and the relation between the impact load and fatigue life is almost linear. Stress-based life-prediction model is proposed for the mixed mode failure. The second type of failure, interface failure between the Ni(P) layer and the solder, occurs under a high-load condition. Fatigue life is shorter in the second type of failure than in the mixed mode failure. Brittleness of the interface reduces the impact-fatigue life.     

Hygrothermal Delaminations in Lead-Free Solder Reflow of Electronic Packages

The use of environmentally friendly lead-free solder in electronic assembly requires a higher process temperatures that double the saturated steam pressure inside the electronic package. We studied the interfacial delamination fractures created by the trapped steam inside the defect voids in packages by computationally modeling the steam diffusion and evaporation processes and the hygrothermal fracture behaviors. These results were compared with results from the conventional saturated steam pressure approach. The comparisons revealed that the saturated steam approach is appropriate for small defects, while the evaporative-diffusion approach is suited for delamination analyses of small and large defects. Our results showed that the strain energy release rate increased with initial defect growth, but reached a defect-size independent plateau when the defect had grown larger than the temperature-dependent critical defect size. To control delamination in packages undergoing lead-free solder reflow, the interfacial fracture energy release rate should be engineered to be above this plateau by controlling the interfacial adhesion, and the applied strain energy release rate should be reduced by reducing the diffusion and evaporation rate of water in the materials.     

Thermal fatigue effects on the temperature distribution inside IGBT modules for zone engine aeronautical applications

This work examines the thermal fatigue effects on the temperature distribution inside IGBT modules for aeronautical applications. Exactly, they are used in a very different application where temperature cycling due to the working environment is the most limiting fact. In this case, it is concluded that solder delamination does not present any restriction to module lifetime at short term (up to 60% of total delaminated area). In addition, it is proposed only determining the delaminated area behind devices, which is the main responsible of the thermal temperature increase.     

Interface delamination analysis of TQFP package during solder reflow

Interface delamination during solder reflow is a critical reliability problem for the plastic IC packages. The main objective of this study is to apply modified virtual crack closure method (MVCCM) for the analysis of interface delamination between the leadframe pad and the encapsulant during a lead-free solder reflow after the level 1 moisture preconditioning. In this study, the moisture diffusion parameters and the coefficient of moisture expansion (CME) of two different epoxy molding compounds (EMC) are characterized for moisture diffusion analysis and the deformation analysis due to hygroscopic swelling. At the same time, the entire thermal and moisture history of Thin Quad Flat Pack (TQFP) package is simulated from the start of level 1 moisture preconditioning (85 °C/85%RH for 168 h) to subsequent exposure to a lead-free solder reflow process. Finally, the transient development of the stress intensity factors due to thermal stress only K_t, hygrostress only K_h, vapor pressure only K_p and combined energy release rate G_tot are computed and studied by using MVCCM. Based on the calculated stress intensity factors and energy release rates, it seems that for the EMC, the Young’s modulus, moisture diffusion coefficient, CME and adhesion strength with leadframe at high temperature appear to be the most significant variables for the MSL performance of TQFP package and this matches well with the experimental finding.