A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Impacts of additive uniaxial strain on hole mobility in bulk Si and strained-Si p-MOSFETs

Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained-Si (s-Si) p-MOSFETs (metal-oxide-semiconductor field-effect transistors) along <110> and <100> channel directions. In bulk Si, a mobility enhancement peak is found under uniaxial compressive strain in the low vertical field. The combination of (100) direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the (110) direction, opposite to the situation in bulk Si. But the combinational strain experiences a gain loss at high field, which means that uniaxial compressive strain may still be a better choice. The mobility enhancement of SiGe-induced strained p-MOSFETs along the (110) direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.     

单轴附加应变对体硅及应变硅p-MOSFETs空穴迁移率的影响

Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained- Si（s-Si）p-MOSFETs（metal-oxide-semiconductor field-effect transistors）along 110 and 100 channel directions. In bulk Si,a mobility enhancement peak is found under uniaxial compressive strain in the low vertical field.The combination of 100 direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the 110 direction,opposite to the situation in bulk Si.But the combinational strain experiences a gain loss at high field,which means that uniaxial compressive strain may still be a better choice.The mobility enhancement of SiGe-induced strained p-MOSFETs along the 110 direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.     

P型张应变Si/SiGe量子阱红外探测器的能带设计

提出P型张应变Si/SiGe量子阱红外探测器(QWIP)结构,应用k·P方法计算应变Si/SiGe量子阱价带能带结构和应变SiGe合金空穴有效质量.结果表明量子阱中引入张应变使轻重空穴反转,基态为有效质量较小的轻空穴态,因此P型张应变Si/SiGe QWIP与n型QWIP相比具有更低的暗电流;而与P型压应变或无应变QWIP相比光吸收和载流子输运特性具有较好改善.在此基础上讨论了束缚态到准束缚态子带跃迁型张应变p-Si/SiGe QWIP的优化设计.     

Fully depleted n-MOSFETs on supercritical thickness strained SOI

Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO/sub 2/ from relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically associated with exceeding this limit.     

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and <110> channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.     

The study of hot-carrier stress on poly-Si TFT employing C-V measurement

The degradation of n-type and p-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) due to hot-carrier stress was investigated by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide of TFTs are not affected by a small-applied signal, whereas the trap states in the bandgap respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. The capacitance (C/sub GS/) between the source and the gate, as well as the capacitance (C/sub GD/) between the drain and the gate, were measured. The difference between the C/sub GD/ and the C/sub GS/ indicates the location of degradation in the TFT. Our experimental results showed that the degradation of n-type TFTs was caused by additional trap states in the grain boundary, whereas the degradation of p-type TFTs was caused by electron trapping into the gate oxide.     

Changes of Electrical Characteristics for AlGaN/GaN HEMTs Under Uniaxial Tensile Strain

This letter investigates the characteristics of unpassivated AlGaN/GaN high-electron mobility transistors (HEMTs) under uniaxial tensile strain. Mechanical stress can produce additional charges that change the HEMT channel current. This phenomenon is dependent upon gate orientation and may be the result of the piezoelectric effect and changes in electron mobility due to the applied uniaxial stress. In addition, results show that tensile strain reduces the transient current, which is likely due to the additional donorlike surface states created through the piezoelectric effect.      

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

Charge trapping in ultrathin hafnium oxide

The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/.     

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

Large differences in the experimentally observed strain-induced threshold-voltage shifts for uniaxial and biaxial tensile-stressed silicon (Si) n-channel MOSFETs are explained and quantified. Using the deformation potential theory, key quantities that affect threshold-voltage (electron affinity, bandgap, and valence band density of states) are expressed as a function of strain. The calculated threshold-voltage shift is in agreement with uniaxial wafer bending and published biaxial strained-Si on relaxed-Si/sub 1-x/Ge/sub x/ experimental data , and explains the technologically important observation of a significantly larger (>4x) threshold-voltage shift for biaxial relative to uniaxial stressed MOSFETs. The large threshold shift for biaxial stress is shown to result from the stress-induced change in the Si channel electron affinity and bandgap. The small threshold-voltage shift for uniaxial process tensile stress is shown to result from the n/sup +/ poly-Si gate in addition to the Si channel being strained and significantly less bandgap narrowing.     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

(111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High- $k$ MISFETs

We have proposed a (111)-faceted metal source and drain (S/D) with a metal gate and a high-k gate dielectric for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The metal S/D is formed by epitaxially grown nickel disilicide. N-type or p-type dopants are segregated in the atomically flat metal/Si interfaces that help to reduce the effective Schottky barrier height between the epitaxial metal and silicon. Therefore, a single type of metal S/D can work for both n-type and p-type MISFETs. The dopant segregation is realized by an ion implantation into the epitaxial silicides and a subsequent low-temperature annealing. Operations of 6-nm-long n-type and p-type silicon-on-insulator MISFETs that came with a fully silicided gate electrode and a high-k gate dielectric were experimentally demonstrated. The excellent short-channel effect immunity due to the trapezoidal channel was also verified by numerical simulation.     

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.     

In search of "Forever," continued transistor scaling one new material at a time

This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching /spl sim/1 in nanoscale planar MOSFETs.     

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

A novel low-voltage N-channel heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) with p-type doped SiGe body

A novel N-channel Si/SiGe heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) has been proposed and fabricated. The Si/SiGe N-HDTMOS consists of an unstrained surface Si channel and heavily p-type doped SiGe body. The potential of the conduction band edge of the surface Si channel can be lowered by introducing a heavily p-type doped SiGe layer into a suitable position in the body region. As a result, the N-HDTMOS shows a threshold voltage reduction and a body effect factor (/spl gamma/) enhancement while keeping high doping concentration in the SiGe layer. The fabricated SiGe N-HDTMOS exhibits superior properties, that is, 0.1 V reduction of V/sub th/, 1.5 times enhancement of /spl gamma/, and 1.3 times saturated current, as compared with those of Si N-DTMOS.     

Effects of Mechanical Strain on Characteristics of Polycrystalline Silicon Thin-Film Transistors Fabricated on Stainless Steel Foil

The effects of uniaxial tensile strain on the performance of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported. Longitudinal strain increases the electron mobility and decreases the hole mobility, while transverse strain decreases the electron mobility and slightly decreases the hole mobility. Under longitudinal strain the off current decreases for both NMOS and PMOS TFTs and shifts in threshold voltage and substhreshold slope are observed for p-channel TFTs. A strong dependence on channel length for both electron and hole mobilities under longitudinal strain indicates the presence of a series resistance. For poly-Si TFTs, the mobility changes under strains are related to the strain effects on single crystalline silicon devices.