Hot carrier-induced SOI MOSFET degradation under AC stressconditions

The hot-carrier-induced device degradation in partially depleted silicon-on-insulator (SOI) devices has been investigated under AC stress conditions. The device degradation of both floating-body SOI devices and body contacted SOI devices have been measured and analyzed for different AC stress frequencies and gate bias voltages. Possible degradation mechanisms are suggested     

Physical Mechanisms behind the Field‐Cycling Behavior of HfO2‐Based Ferroelectric Capacitors

Novel hafnium oxide (HfO₂)‐based ferroelectrics reveal full scalability and complementary metal oxide semiconductor integratability compared to perovskite‐based ferroelectrics that are currently used in nonvolatile ferroelectric random access memories (FeRAMs). Within the lifetime of the device, two main regimes of wake‐up and fatigue can be identified. Up to now, the mechanisms behind these two device stages have not been revealed. Thus, the main scope of this study is an identification of the root cause for the increase of the remnant polarization during the wake‐up phase and subsequent polarization degradation with further cycling. Combining the comprehensive ferroelectric switching current experiments, Preisach density analysis, and transmission electron microscopy (TEM) study with compact and Technology Computer Aided Design (TCAD) modeling, it has been found out that during the wake‐up of the device no new defects are generated but the existing defects redistribute within the device. Furthermore, vacancy diffusion has been identified as the main cause for the phase transformation and consequent increase of the remnant polarization. Utilizing trap density spectroscopy for examining defect evolution with cycling of the device together with modeling of the degradation results in an understanding of the main mechanisms behind the evolution of the ferroelectric response.     

Reliability issues of GaN based high voltage power devices

GaN based power devices for high efficiency switching applications in modern power electronics are rapidly moving into the focus of world wide research and development activities. Due to their unique material properties GaN power devices are distinguished by featuring high breakdown voltages, low on-state resistances and fast switching properties at the same time. Finally, these properties are the consequences of extremely high field and current densities that are possible per unit device volume or area. Therefore, in order to obtain very high performance, the material itself is stressed significantly during standard device operation and any imperfection may lead to wear out and reliability problems. Thus material quality, the specific epitaxial design as well as the device topology will directly influence device performance, reliability and mode of degradation. The paper will mainly discuss those degradation mechanisms that are especially due to the specific material combinations used in GaN based high voltage device technology such as epitaxial layer design, chip metallization, passivation schemes and general device topology and layout. It will then discuss technological ways towards engineering reliability into these devices. Generally, device designs are required that effectively minimize high field regions in the internal device or shift them towards less critical locations. Furthermore, an optimized thermal design in combination with suitable chip mounting technologies is required to enable maximum device performance.     

Reliability aspects of thermal micro-structures implemented on industrial 0.8 μm CMOS chips

This paper discusses the reliability characterization of thermal micro-structures implemented on industrial 0.8 μm CMOS chips. Various degradation and failure mechanisms are identified and evaluated under high temperature operation. At high temperatures the mechanisms are many and varied, and co-incidental thermally-induced mechanical defects are found in both the poly-Si heater and the poly-Si temperature sensor, along with temperature- and current-enhanced interlayer diffusion degradation of the heater contacts. Local reduction in the device thermal capacity by using silicon micro-machining can be expected to hold the promise of a number of significant advantages, especially for limiting current stressing of the contact regions. The results can be used to optimize the design of thermally based micro-sensors on CMOS chips, such as CMOS compatible chemoresistive gas sensors.     

Procedure for evaluation of thermal management requirements in a laser diode structure

Temperature is either a direct catalyst or a precipitating factor in several common laser diode degradation mechanisms including dark-line defects, catastrophic optical destruction, metal diffusion and electrode delamination. This strong correlation between device temperature and performance degradation demonstrates the need for an efficient thermal management strategy. We have adopted a commonly used heat generation model to perform a finite element analysis to compute steady-state and transient thermal profiles for a laser diode structure. The flexibility of the FE model is utilized in performing a parametric study of selected variables affecting temperature in the structure. Taguchi principles are used in the set-up and analysis of this model, and quantitative correlations between the selected variables and temperature are derived. The combined interaction expression is then modeled as an optimization function that may be applied in thermal management analysis. The approach demonstrated here conforms to a general methodology for the development of physics of failure models for degradation in optoelectronic devices.     

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO₂ barrier.     

Stress induced degradation features of very thin gate oxides

The degradation features of very thin gate oxide after Fowler-Nordheim stress have been studied. Bulk oxide, cathodic and anodic regions have been analysed from the charge build-up point of view, as well as the stress induced generation of Si/SiO₂ fast interface state density. A physical interpretation of experimental results has been proposed, involving two types of stress induced positive charge building up at interface regions. It is shown that a critical oxide thickness exists, under which the degradation mechanisms could be considerably different.     

Observation of oxide breakdown and its effects on thecharacteristics of ultra-thin-oxide nMOSFET's

Ultra-thin gate oxide breakdown in nMOSFET's has been studied for an oxide thickness of 1.5 nm using constant voltage stressing. The pre- and post-oxide breakdown characteristics of the device have been compared, and the results have shown a strong dependence on the breakdown locations. The oxide breakdown near the source/drain-to-gate overlap regions was found to be more severe on the post-breakdown characteristics of the device than breakdown in the channel. This observation may be related to the dependence of breakdown on the distribution of electric field and areas of different regions within the nMOSFET under stress     

Modeling and simulation of hot-carrier-induced device degradationin MOS circuits

The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions     

Optimization of LDD devices for cryogenic operation

The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K     

Performance characteristics of high-brightness, CW, diode laser arrays

Recently developed, high-brightness diode laser arrays have been tested at 50°C at output powers of 0.5 W CW and 1.0W CW from 100?m- and 200?m-wide active regions, respectively. The extrapolated lifetimes at room temperature exceed 40000 h. The maximum CW power output prior to catastrophic degradation of the facets is 2.0 W for the 100?m device and greater than 3 W for the 200?m-aperture device.     

Characterisation of degradation mechanisms in resonant tunnelling diodes

By applying high voltage transmission line pulses and elevated temperatures we stressed resonant tunnelling diodes (RTD). The influence of the stress on the electrical characteristics of these devices is shown and the possible degradation mechanisms are identified. Various RTDs from different semiconductor systems (arsenides and antimonides) have been fabricated using molecular beam epitaxy. We report the influence of the growth temperatures of these RTDs on the device degradation.     

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.     

NBTI degradation in STI-based LDMOSFETs

NBTI degradation in STI-based LDMOSFETs has been investigated by multi-region DCIV spectroscopy (MR-DCIV), a non-destructive and sensitive method to probe the interface states on channel, accumulation and STI region. A unified MR-DCIV current model was proposed based on its independency to the forward bias and temperature. Under the same negative gate stress condition, MR-DCIV current degradation was compared for nLDMOSFET and pLDMOSFET. Much larger MR-DCIV current shift was observed at channel and accumulation region with thin gate oxide thickness, indicating interface states generation at related regions. Our results show that more significant degradation for multi-finger device was consistent with NBTI degradation mechanism. High voltage device design with thermal management consideration is of crucial importance to guaranteeing the device performance and reliability.     

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.     

Degradation mechanism understanding of NLDEMOS SOI in RF applications

The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation.     

Selective oxidation fin channel MOSFETs with low source=drain series resistance

Novel selective oxidation fin channel MOSFETs (SoxFETs) have been developed for fabricating fin channel MOSFETs with low source/drain (S/D) series resistance. Using this technique, SoxFETs have the surround gate structure and gradually increased S/D extension regions. The new structure demonstrates a 74% reduction in S/D series resistance compared with the control device. It was also found that the SoxFET behaved better than the control device in current drivability by suppressing subthreshold swing and drain induced barrier lowering characteristic degradation.     

VLSI MOSFETs lifetime reduction caused by impedance mismatch

In this letter, the impact of impedance mismatch between on-die CMOS drivers and driven transmission lines upon device reliability has been studied. The signal waveforms corrupted by the impedance mismatch, experimentally measured at the far-end of the transmission line (45 nm CMOS technology test chip), have been taken as a basis for calculations of Age parameters from the Berkeley reliability tools model. The results reveal that the impedance mismatch accelerates the device degradation due to time-dependent dielectric breakdown, negative bias temperature instability and hot carrier injection wearout mechanisms. Therefore, the impedance mismatch should be regarded also as a reliability issue.     

Degradation mechanisms in organic photovoltaic devices

In the present review, the main degradation mechanisms occurring in the different layer stacking (i.e. photoactive layer, electrode, encapsulation film, interconnection) of polymeric organic solar cells and modules are discussed. Bulk and interfacial, as well as chemical and physical degradation mechanisms are reviewed, as well as their implications and external or internal triggers. Decay in I-V curves in function of time is usually due to the combined action of sequential and interrelated mechanisms taking place at different locations of the device, at specific kinetics. This often makes the identification of specific root causes of degradation challenging in non-model systems. Additionally, constant development and refinement in terms of type and combination of materials and processes render the ranking of degradation mechanisms as a function of their probability of occurrence and their detection challenging.However, it clearly appears that for the overall stability of organic photovoltaic devices, the actual photoactive layer, as well as the properties of the barrier and substrate (e.g. cut of moisture and oxygen ingress, mechanical integrity), remain critical. Interfacial stability is also crucial, as a modest degradation at the level of an interface can quickly and significantly influence the overall device properties.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.