大内存大学问 笔记本电脑内存指南

笔记本电脑内存速度、容量对其性能有着重大的影响。传统计算机架构中，处理器负责运算工作，内存则是工作数据暂存的区域，硬盘是储存、读取数据的地方。     

内存天下

容量的迅速增加和价格的持续走低,让基于闪存的存储卡跳出了 PDA 和数码相机这样"小儿科"的应用领域,现在就连数据存储大户数码摄像机也看上了它     

XDR内存领导高速内存未来走向

随着视频娱乐系统对3D效能、高分辨率输出的需求确立,XDR这种专门为此类应用而设计的新世代高速内存技术出货量也开始获得业界看好.根据XDR技术授权厂商Rambus日前所发表的新闻稿,XDR内存的累计出货量已经超过2500万颗,而且包含三星、尔必达、奇梦达等主要内存供货商都已经开始量产XDR内存颗粒.     

内存初探

<正> 内存(俗称内存条)作为计算机中的主存储器,是专门为CPU所设置的工作空间,主要用于暂时存储CPU运行中的操作程序和数据。在电气结构上,内存的数据线挂接在北桥芯片上,并通过前端总线与CPU交换数据。在计算机硬件系统中,内存对计算机的性能和运行稳定性影响甚大,我们经常遭遇到的电脑死机、显示器不能点亮、讨厌的蓝屏以及使用整合主     

Delphi内存管理与内存泄漏探析

综述了Delphi环境下动态内存分配与释放的方法，分析了内存泄漏的可能原因，并列举了开发“智能型远程作业系统”过程中出现的有关内存泄漏的几个实例。     

内存综述

当今的计算机，CPU的速度越来越快、性能越来越高。作为计算机系统中最重要的资源之一的内存的容量也大幅增加，目前主流内存的配置已是32M，有的甚至已达64M或128M，是IBM公司推出的第一台PC机16KB的几千倍，速度也有了很大的提高。但内存速度方面的增长却远远落于CPU的发展，已成为计算机速度和性能进一步提高的瓶颈（Bottleneck）。CPU芯片的厂商通过向芯片增加晶体管的方法，如增加数学运算单元，可以很容易地提高CPU的性能，增加两倍的ALU几乎可以获得两倍的芯片速度。而对于内存芯片来说增加更多的晶体管，只意味着能容纳…     

内存随想曲

应用软件或游戏常会标识出运行时所需的最低系统配置。不过多数使用者应该都有过这样的经验,若只是依据这种标准运行程序,性能表现上是远远不能满足要求的,其中主要的原因是内存容量不足,其他的才是微处理器速度或是相关外设的配合问题。那么购买电脑时究竟该配备多少内存才够用呢?想信这是许多人心中长久以来的疑惑,也是一个相当有趣的问题。在目前视为主流的操作系统的环境下,内存的多少事实上会影响到系统的运行性能,但性能增长的幅度与内存倍增间存在什么关系,则又是另一个值得探究的问题,也直接决定着该购买多少内存。在这次的测试中,我们选择了32、64、128与256MB四种不同容量的内存,分别针对应用程序,游戏,图像处理等不同需求,测试倍增内存与系统性能增加间的关系,并讨论测试结果所代表的含意。希望通过详细的测试与说明,能带给读者一个比较明确的概念与采购建议,且在能符合经济性的原则下,购买适量的内存,同时又能兼顾日常工作所需。     

内存市场行情

型号参考价(元)型号参考价(元)型号参考价(元)三星64M(RAMBUS)150,HY 32M(PC133)25KINGSTON 128M(笔记本)175三星128M(RA材BUS)、340新款KINGHORSE 64M(笔记本)442KINGSTON 64M(笔记本)95三星256M(DDR)265KINGHORSE 128M(笔记本)196KINGSTON 256M(RAMBUS)855三星128M(DDR)135KING}10RSE 256M(笔记本)595KINGSTON 128M(以MBUS)365GL2000 256M(笔记本PC133)290KINGL{ORSE 64M(笔记本)134KINGSTON 512M(PC133)585GL200O 128M(笔记本PC133)160KINGHORSE 256M(台式机)287KINGSTON 2…     

内存新贵——Winward KTI PC133内存

毫无疑问,在电脑硬件市场上再没有任何产品的变动能像内存这样令人惊心动魄了,从过去的疯狂上涨到现在的直线下跌,无数的用户和商家都经历了大喜大悲。不过,众多的内存生产厂家并没有因为目前内存价格的下跌而放弃这个市场,而是在努力推出技术更新,性能更高的新产品。而本次PC Computing中国易用性实验室对胜壹科技生产的Winward KTIPC133内存进行了评测。     

Symbiotic Dynamic Memory Balancing for Virtual Machines in Smart TV Systems

Smart TV is expected to bring cloud services based on virtualization technologies to the home environment with hardware and software support. Although most physical resources can be shared among virtual machines (VMs) using a time sharing approach, allocating the proper amount of memory to VMs is still challenging. In this paper, we propose a novel mechanism to dynamically balance the memory allocation among VMs in virtualized Smart TV systems. In contrast to previous studies, where a virtual machine monitor (VMM) is solely responsible for estimating the working set size, our mechanism is symbiotic. Each VM periodically reports its memory usage pattern to the VMM. The VMM then predicts the future memory demand of each VM and rebalances the memory allocation among the VMs when necessary. Experimental results show that our mechanism improves performance by up to 18.28 times and reduces expensive memory swapping by up to 99.73% with negligible overheads (0.05% on average).     

基于扩展控制流图的片上存储器分配策略

本文提出一种基于扩展控制流图(ECFG)的片上存储器(Scratch-Pad Memory,SPM)分配策略,该策略首先把程序划分为全局变量、全局堆栈、指令块等节点,用包含节点和节点间关系的ECFG来描述应用程序,接着采用考虑了节点间关系的改进的背包算法把选中的节点分配到SPM中.实验表明该策略比采用单纯背包算法的SPM分配策略减少应用程序执行时间11%,比不使用SPM时减少56%,大大提高了SoC存储子系统的性能.     

CSP引发内存封装技术的革命

简要介绍了几种内存芯片封装技术的特点。CSP是内存芯片封装技术的新概念,它的出现促进内存芯片的发展和革新,并将成为未来高性能内存的最佳选择。     

基于新型非易失存储器的混合内存架构的内存管理机制

随着互联网和云计算技术的迅猛发展,现有动态随机存储器（Dynamic Random Access Memory,DRAM）已无法满足一些实时系统对性能、能耗的需求.新型非易失存储器（Non-Volatile Memory,NVM）的出现为计算机存储体系的发展带来了新的契机.本文针对NVM和DRAM混合内存系统架构,提出一种高效的混合内存页面管理机制.该机制针对内存介质写特性的不同,将具有不同访问特征的数据页保存在合适的内存空间中,以减少系统的迁移操作次数,从而提升系统性能.同时该机制使用一种两路链表使得NVM介质的写操作分布更加均匀,以提升使用寿命.最后,本文在Linux内核中对所提机制进行仿真实验.并与现有内存管理机制进行对比,实验结果证明了所提方法的有效性.     

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Line-pixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.

CSP引发内存封装技术的革命

简要介绍了几种内存芯片封装技术的特点.CSP是内存芯片封装技术的新概念,它的出现促进内存芯片的发展和革新,并将成为未来高性能内存的最佳选择.     

一种构建双端口共享存储器的方法

基于双CPU共享RAM技术,从经济实用的角度出发,提出了一种利用单端口存储器构建双端口共享存储器的方法。根据62256单端口存储器的工作原理和结构设计特点,利用单向缓冲器芯片74ALS244对存储器的地址总线、控制总线进行扩展,利用双向缓冲器芯片74ALS245对存储器的数据总线进行扩展,存储器的地址线、数据线和控制线分别由单路变为双路,再通过选通信号实现对各路总线的读写控制。经扩展的单端口存储器可实现双端口存储器的全部功能,具有成本低、容量大、性能稳定的优点,可广泛应用于硬件设计。     

Investigation of Time–Dependent Resistive Switching Behaviors of Unipolar Nonvolatile Organic Memory Devices

Organic resistive memory devices are one of the promising next‐generation data storage technologies which can potentially enable low‐cost printable and flexible memory devices. Despite a substantial development of the field, the mechanism of the resistive switching phenomenon in organic resistive memory devices has not been clearly understood. Here, the time–dependent current behavior of unipolar organic resistive memory devices under a constant voltage stress to investigate the turn‐on process is studied. The turn‐on process is discovered to occur probabilistically through a series of abrupt increases in the current, each of which can be associated with new conducting paths formation. The measured turn‐on time values can be collectively described with the Weibull distribution which reveals the properties of the percolated conducting paths. Both the shape of the network and the current path formation rate are significantly affected by the stress voltage. A general probabilistic nature of the percolated conducting path formation during the turn‐on process is demonstrated among unipolar memory devices made of various materials. The results of this study are also highly relevant for practical operations of the resistive memory devices since the guidelines for time‐widths and magnitudes of voltage pulses required for writing and reading operation can be potentially set.     

嵌入式存储器的内建自修复设计

目前，关于嵌入式存储器的内建自测试（MBIST）技术已经日趋成熟。基于这种背景．研究了一种高效的内建自修复（MBISR）方法，试验表明它具有低面积开销和高修复率等优点，保证了嵌入式存储器不仅可测．而且可修复。极大地提高了芯片的成品率。     

A Flexible Programmable Memory BIST for Embedded Single‐Port Memory and Dual‐Port Memory

Programmable memory built‐in self‐test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single‐port memory and dual‐port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.